drm/amd/display: Add fallback to prefetch mode 1 if 0 fails

[Why]
In some cases, prefetch mode 0 is unsupported but prefetch 1 is
supported. Due to previous change always forcing prefetch mode to 0, we
are failing bandwidth validation in cases where we should not.

[How]
By default try prefetch mode 0 but in the case validation fails, attempt
to do prefetch mode 1 to see if it is supported.

Signed-off-by: Isabel Zhang <isabel.zhang@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 5ae3419682c838051d605c123d16512d90125407..3d8b0875e905ff80d6c43c6490dffaa86074e03e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -301,9 +301,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
        .xfc_bus_transport_time_us = 4,
        .xfc_xbuf_latency_tolerance_us = 4,
        .use_urgent_burst_bw = 1,
-       .num_states = 8,
-       .allow_dram_self_refresh_or_dram_clock_change_in_vblank
-                       = dm_allow_self_refresh_and_mclk_switch
+       .num_states = 8
 };
 
 #ifndef MAX
@@ -1199,11 +1197,29 @@ static bool dcn21_fast_validate_bw(
                out = true;
                goto validate_out;
        }
-
+       /*
+        * DML favors voltage over p-state, but we're more interested in
+        * supporting p-state over voltage. We can't support p-state in
+        * prefetch mode > 0 so try capping the prefetch mode to start.
+        */
+       context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
+                               dm_allow_self_refresh_and_mclk_switch;
        vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
 
-       if (vlevel > context->bw_ctx.dml.soc.num_states)
-               goto validate_fail;
+       if (vlevel > context->bw_ctx.dml.soc.num_states) {
+               /*
+                * If mode is unsupported or there's still no p-state support then
+                * fall back to favoring voltage.
+                *
+                * We don't actually support prefetch mode 2, so require that we
+                * at least support prefetch mode 1.
+                */
+               context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
+                                       dm_allow_self_refresh;
+               vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
+               if (vlevel > context->bw_ctx.dml.soc.num_states)
+                       goto validate_fail;
+       }
 
        vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index 367c82b5ab4c17374b065ae7dc1939b795b599b7..86ff24dffc3efbc7e4830c53015d0f979b8f0249 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -5477,7 +5477,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
                }
        }
 
-       if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
+       if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0 && PrefetchMode == 0) {
                *DRAMClockChangeSupport = dm_dram_clock_change_vactive;
        } else if (((mode_lib->vba.SynchronizedVBlank == true
                        || mode_lib->vba.TotalNumberOfActiveOTG == 1