Merge tag 'riscv-for-linus-4.17-mw0' of git://git.kernel.org/pub/scm/linux/kernel...

Pull RISC-V updates from Palmer Dabbelt:
 "This contains the new features we'd like to incorporate into the
  RISC-V port for 4.17. We might have a bit more stuff land later in the
  merge window, but I wanted to get this out earlier just so everyone
  can see where we currently stand.

  A short summary of the changes is:

   - We've added support for dynamic ftrace on RISC-V targets.

   - There have been a handful of cleanups to our atomic and locking
     routines. They now more closely match the released RISC-V memory
     model draft.

   - Our module loading support has been cleaned up and is now enabled
     by default, despite some limitations still existing.

   - A patch to define COMMANDLINE_FORCE instead of COMMANDLINE_OVERRIDE
     so the generic device tree code picks up handling all our command
     line stuff.

  There's more information in the merge commits for each patch set"

* tag 'riscv-for-linus-4.17-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux: (21 commits)
  RISC-V: Rename CONFIG_CMDLINE_OVERRIDE to CONFIG_CMDLINE_FORCE
  RISC-V: Add definition of relocation types
  RISC-V: Enable module support in defconfig
  RISC-V: Support SUB32 relocation type in kernel module
  RISC-V: Support ADD32 relocation type in kernel module
  RISC-V: Support ALIGN relocation type in kernel module
  RISC-V: Support RVC_BRANCH/JUMP relocation type in kernel modulewq
  RISC-V: Support HI20/LO12_I/LO12_S relocation type in kernel module
  RISC-V: Support CALL relocation type in kernel module
  RISC-V: Support GOT_HI20/CALL_PLT relocation type in kernel module
  RISC-V: Add section of GOT.PLT for kernel module
  RISC-V: Add sections of PLT and GOT for kernel module
  riscv/atomic: Strengthen implementations with fences
  riscv/spinlock: Strengthen implementations with fences
  riscv/barrier: Define __smp_{store_release,load_acquire}
  riscv/ftrace: Add HAVE_FUNCTION_GRAPH_RET_ADDR_PTR support
  riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support
  riscv/ftrace: Add ARCH_SUPPORTS_FTRACE_OPS support
  riscv/ftrace: Add dynamic function graph tracer support
  riscv/ftrace: Add dynamic function tracer support
  ...

diff --cc arch/riscv/Kconfig
Simple merge

diff --cc scripts/recordmcount.pl
index c74ecc6504e8a172525fb5e34e0ca83c5e7059aa,d44d55db7c0675b28dac5e5cb8749d9d0265fa31..191eb949d52c1e01dd5b33e2fd7be2ad7b471d6a
--- 1/scripts/recordmcount.pl
--- 2/scripts/recordmcount.pl
+++ b/scripts/recordmcount.pl
@@@ -368,6 -368,19 +368,11 @@@ if ($arch eq "x86_64") 
  } elsif ($arch eq "microblaze") {
      # Microblaze calls '_mcount' instead of plain 'mcount'.
      $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s_mcount\$";
 -} elsif ($arch eq "blackfin") {
 -    $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s__mcount\$";
 -    $mcount_adjust = -4;
 -} elsif ($arch eq "tilegx" || $arch eq "tile") {
 -    # Default to the newer TILE-Gx architecture if only "tile" is given.
 -    $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s__mcount\$";
 -    $type = ".quad";
 -    $alignment = 8;
+ } elsif ($arch eq "riscv") {
+     $function_regex = "^([0-9a-fA-F]+)\\s+<([^.0-9][0-9a-zA-Z_\\.]+)>:";
+     $mcount_regex = "^\\s*([0-9a-fA-F]+):\\sR_RISCV_CALL\\s_mcount\$";
+     $type = ".quad";
+     $alignment = 2;
  } else {
      die "Arch $arch is not supported with CONFIG_FTRACE_MCOUNT_RECORD";
  }