feat(ti): disable L2 dataless UniqueClean evictions

Do this early before we enable caching as a workaround for ARM A72
Errata #854172.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ic878fdb49e598da0ea6ade012712f8f57023678e

diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S
index 6742e74f1e9ce79484988628c80458179b4546a2..da94c16442be1146014b821c40538bd73828d43d 100644 (file)
--- a/plat/ti/k3/common/k3_helpers.S
+++ b/plat/ti/k3/common/k3_helpers.S
@@ -118,6 +118,12 @@ a72:
        orr x0, x0, #CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE
        orr x0, x0, #CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE
        msr CORTEX_A72_L2CTLR_EL1, x0
+
+       mrs x0, CORTEX_A72_L2ACTLR_EL1
+       /* Enable L2 UniqueClean evictions with data */
+       orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN
+       msr CORTEX_A72_L2ACTLR_EL1, x0
+
        isb
        ret
 endfunc plat_reset_handler