sunxi: prcm: Add a few registers

H6 and H616 SPL code has a few writes to unknown PRCM registers. Now
that we know what they are, let's replace magic offsets with proper
register names.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
index 5f636e83845a862ddeec9a20574fb2dd160826b3..fd63d3aad8399071f0fab63ee79cfca97962997e 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
@@ -37,8 +37,18 @@ struct sunxi_prcm_reg {
        u32 w1_gate_reset;      /* 0x1ec */
        u8 res10[0x1c];         /* 0x1f0 */
        u32 rtc_gate_reset;     /* 0x20c */
+       u8 res11[0x34];         /* 0x210 */
+       u32 pll_ldo_cfg;        /* 0x244 */
+       u8 res12[0x8];          /* 0x248 */
+       u32 sys_pwroff_gating;  /* 0x250 */
+       u8 res13[0xbc];         /* 0x254 */
+       u32 res_cal_ctrl;       /* 0x310 */
+       u32 ohms200;            /* 0x314 */
+       u32 ohms240;            /* 0x318 */
+       u32 res_cal_status;     /* 0x31c */
 };
 check_member(sunxi_prcm_reg, rtc_gate_reset, 0x20c);
+check_member(sunxi_prcm_reg, res_cal_status, 0x31c);
 
 #define PRCM_TWI_GATE          (1 << 0)
 #define PRCM_TWI_RESET         (1 << 16)

diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index a947463e0a53d883733c3fbd7352ae2e456c5812..e5846e6381ff42a468c81b172fe1a3d7354d9269 100644 (file)
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -9,10 +9,12 @@ void clock_init_safe(void)
 {
        struct sunxi_ccm_reg *const ccm =
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       struct sunxi_prcm_reg *const prcm =
+               (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
 
        /* this seems to enable PLLs on H616 */
        if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
-               setbits_le32(SUNXI_PRCM_BASE + 0x250, 0x10);
+               setbits_le32(&prcm->sys_pwroff_gating, 0x10);
 
        clock_set_pll1(408000000);
 

diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index d05375c902772d254d8749948c1a3f38ebe5b6d7..b332f3a3e4aae363162cc5ccf866eee009a504cd 100644 (file)
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -12,6 +12,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/dram.h>
 #include <asm/arch/cpu.h>
+#include <asm/arch/prcm.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
 #include <linux/kconfig.h>
@@ -665,6 +666,8 @@ unsigned long sunxi_dram_init(void)
 {
        struct sunxi_mctl_com_reg * const mctl_com =
                        (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+       struct sunxi_prcm_reg *const prcm =
+               (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
        struct dram_para para = {
                .clk = CONFIG_DRAM_CLK,
 #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
@@ -680,9 +683,8 @@ unsigned long sunxi_dram_init(void)
 
        unsigned long size;
 
-       /* RES_CAL_CTRL_REG in BSP U-boot*/
-       setbits_le32(0x7010310, BIT(8));
-       clrbits_le32(0x7010318, 0x3f);
+       setbits_le32(&prcm->res_cal_ctrl, BIT(8));
+       clrbits_le32(&prcm->ohms240, 0x3f);
 
        mctl_auto_detect_rank_width(&para);
        mctl_auto_detect_dram_size(&para);

diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 83e8abc2f8d8953c5a2362a59aef0ab2d241b420..454c845a00106638248673c7025fcbaa3e779034 100644 (file)
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -19,6 +19,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/dram.h>
 #include <asm/arch/cpu.h>
+#include <asm/arch/prcm.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
 #include <linux/kconfig.h>
@@ -1001,14 +1002,16 @@ static unsigned long mctl_calc_size(struct dram_para *para)
 
 unsigned long sunxi_dram_init(void)
 {
+       struct sunxi_prcm_reg *const prcm =
+               (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
        struct dram_para para = {
                .clk = CONFIG_DRAM_CLK,
                .type = SUNXI_DRAM_TYPE_DDR3,
        };
        unsigned long size;
 
-       setbits_le32(0x7010310, BIT(8));
-       clrbits_le32(0x7010318, 0x3f);
+       setbits_le32(&prcm->res_cal_ctrl, BIT(8));
+       clrbits_le32(&prcm->ohms240, 0x3f);
 
        mctl_auto_detect_rank_width(&para);
        mctl_auto_detect_dram_size(&para);