dcache_enable();
#endif
}
-
{
return psci_context_id[cpu];
}
-
HYPERCALL2(event_channel_op);
HYPERCALL2(hvm_op);
HYPERCALL2(memory_op);
-
#define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 3, 3)
#define PIN_PE7__ISC_D11 PINMUX_PIN(PIN_PE7, 5, 2)
#define PIN_PE7__G1_TSUCOMP PINMUX_PIN(PIN_PE7, 7, 1)
-
#define _ASM_ARCH_IMXRT_H
#endif /* _ASM_ARCH_IMXRT_H */
-
/* init rockusb device, tell rockusb which device you want to read/write*/
void rockusb_dev_init(char *dev_type, int dev_index);
#endif /* _F_ROCKUSB_H_ */
-
void stm32_flash_latency_cfg(int latency);
#endif /* _ASM_ARCH_STM32F_H */
-
extern int clock_setup(enum periph_clock);
#endif
-
*/
extern unsigned long rom_pointer[];
-
ret
ENDPROC(ccn504_set_aux)
-
else
writel(0, &sfr->ddrcfg);
}
-
# */
obj-y += lowlevel_init.o clock.o cpu.o
-
# */
obj-y += lowlevel_init.o clock.o cpu.o
-
#include <asm/arch-tegra/dc.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/timer.h>
-
extra-y = start.o
obj-y = interrupts.o cpu.o speed.o cpu_init.o
-
} gpio_t;
#endif /* __IMMAP_5307__ */
-
#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
#endif /* mcf5307_h */
-
void sdram_init(void);
#endif /* __JZ4780_DRAM_H__ */
-
sync /* wait for dcbi's to get to ram */
#endif
blr
-
#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
#define XCHAL_SA_NUM_ATMPS 2
#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
#endif /*_XTENSA_CORE_TIE_H*/
-
#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
#define XCHAL_SA_NUM_ATMPS 1
#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
#endif /*_XTENSA_CORE_TIE_H*/
-
#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
#define XCHAL_SA_NUM_ATMPS 1
#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
#endif /*_XTENSA_CORE_TIE_H*/
-
#define DEBUGCAUSE_ICOUNT_BIT 0 /* ICOUNT would incr. to zero */
#endif /* _XTENSA_SPECREG_H */
-
memset((void *)&__bss_start, 0x00, len);
return 0;
}
-
{
return fdt_get_board_model();
}
-
# Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
obj-y += armadillo-800eva.o
-
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
-
====
Set baseboard DIP switch:
S17: 1100XXXX
-
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3200, 400, 100, },
};
-
5. Use one of previous descriptions to re-flash the SPI-NOR as required.
6. Ensure SW1 is returned to "00" to boot from the fuses once done.
-
Because this problem is easy to fall into and difficult to debug
if one doesn't expect it, the linker script provides a link-time
check and fatal error message if the image size exceeds 128 KB.
-
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 2400, 400, 100, },
};
-
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 2400, 1066, },
};
-
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 1600, 1066, },
};
-
DPMAC14 -> PHY4-P1
DPMAC15 -> PHY4-P2
DPMAC16 -> PHY4-P3
-
=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
hugepages=16 mem=2048M'
-
gd->ram_size = imx_ddr_size();
return 0;
}
-
#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
#define CPLD_WRITE(reg, value) \
cpld_write(offsetof(struct cpld_data, reg), value)
-
obj-y := gw_ventana.o gsc.o eeprom.o common.o
obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o
-
int gsc_boot_wd_disable(void);
const char *gsc_get_dtb_name(int level, char *buf, int sz);
#endif
-
return dm_gpio_request(gpio, gpio_name);
}
-
else
env_set("rtc_status", "OK");
}
-
};
size_t display_count = ARRAY_SIZE(displays);
-
return qrio_get_gpio(KM_I2C_DEBLOCK_PORT,
KM_I2C_DEBLOCK_SCL);
}
-
Additional Support Documentation can be found at:
https://support.logicpd.com/
-
# SPDX-License-Identifier: GPL-2.0
obj-y += mt7622_rfb.o
-
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
-
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
obj-$(CONFIG_SOC_JR2) := jr2.o
-
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
obj-$(CONFIG_SOC_OCELOT) := ocelot.o
-
return ret;
return PS7_INIT_SUCCESS;
}
-
#define HNF_BASE (unsigned long)(0x3A200000)
#endif /* _FT_DURIAN_H */
-
#include <dm.h>
#include <asm/io.h>
#include <asm/arch-rockchip/uart.h>
-
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
-
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
-
};
#endif /* _BOARD_SYNOPSYS_AXS10X_H */
-
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3200, 667, },
};
-
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3200, 667, },
};
-
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3200, 667, },
};
-
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3200, 667, },
};
-
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
#endif /* _PRELOADER_PLL_CONFIG_H_ */
-
"versal sub-system",
versal_help_text
)
-
//xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
return PS7_INIT_SUCCESS;
}
-
-
-
-
//xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
return PS7_INIT_SUCCESS;
}
-
-
-
-
//xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
return PS7_INIT_SUCCESS;
}
-
-
-
-
return ret;
return PS7_INIT_SUCCESS;
}
-
"pvblock write addr blk# cnt - read/write `cnt'"
" blocks starting at block `blk#'\n"
" to/from memory address `addr'");
-
U_BOOT_CMD_WITH_SUBCMDS(scp03, "Secure Channel Protocol 03 control", text,
U_BOOT_SUBCMD_MKENT(enable, 1, 1, do_scp03_enable),
U_BOOT_SUBCMD_MKENT(provision, 1, 1, do_scp03_provision));
-
" - id Session ID, passed to W7 (defaults to zero)\n"
);
#endif
-
"print string on lcd-framebuffer",
" <string>"
);
-
#if CONFIG_IS_ENABLED(DFU)
SPL_LOAD_IMAGE_METHOD("DFU", 0, BOOT_DEVICE_DFU, spl_ram_load_image);
#endif
-
-
# pcap stop
# tftpput 0xffffffff80100000 $pcapsize 10.0.2.2:capture.pcap
-
clock-names = "biu", "ciu";
max-frequency = <25000000>;
};
-
compatible = "maxim,ds24xxx";
}
};
-
compatible = "maxim,ds2502";
};
};
-
compatible = "sandbox,w1-eeprom";
}
};
-
compatible = "maxim,ds24xxx";
}
};
-
0xFFF00000 0xFFFFFFFF Bootrom
0x100000000 <DRAM Size>-1 DRAM
-
- NAND: # nand write <load_address> 0 <ATF Size>
- SPI: # sf write <load_address> 0 <ATF Size>
- SD/eMMC: # mmc write <load_address> [0|1] <ATF Size>/<block_size>
-
.post_bind = dm_scan_fdt_dev,
.flags = DM_UC_FLAG_SEQ_ALIAS,
};
-
.ops = &sam9x60_frac_pll_ops,
.flags = DM_FLAG_PRE_RELOC,
};
-
obj-$(CONFIG_CLK_MESON_AXG) += axg.o
obj-$(CONFIG_CLK_MESON_G12A) += g12a.o
obj-$(CONFIG_CLK_MESON_G12A) += g12a-ao.o
-
debug("DDR: HMC init success\n");
return 0;
}
-
: "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
}
-
.probe = hi6220_gpio_probe,
.priv_auto = sizeof(struct gpio_bank),
};
-
-
void nand_deselect(void)
{
}
-
/* send command to mc*/
return mc_send_command(mc_io, &cmd);
}
-
.ops = &mvmdio_ops,
.priv_auto = sizeof(struct mvmdio_priv),
};
-
};
U_BOOT_PCI_DEVICE(octeontx_nic, octeontx_nic_supported);
-
obj-$(CONFIG_NET_OCTEONTX2) += cgx.o nix_af.o nix.o rvu_pf.o \
rvu_af.o rvu_common.o
-
printf(" CGX%d LMAC%d [%s]", lmac->cgx->cgx_id, lmac->lmac_id,
lmac_type_to_str[lmac->lmac_type]);
}
-
}
#endif /* __NPC_H__ */
-
void rvu_get_lfid_for_pf(int pf, int *nixid, int *npaid);
#endif /* __RVU_H__ */
-
void comphy_pcie_unit_general_config(u32 pex_index);
#endif /* _COMPHY_CORE_H_ */
-
(0x3 << UTMI_CHGDTC_CTRL_VSRC_OFFSET)
#endif /* _UTMI_PHY_H_ */
-
.probe = mtk_pinctrl_mt7622_probe,
.priv_auto = sizeof(struct mtk_pinctrl_priv),
};
-
-
.plat_auto = sizeof(struct rk322x_sdram_params),
#endif
};
-
.of_match = raspberrypi_reset_ids,
.ops = &raspberrypi_reset_ops,
};
-
.probe = sti_asc_serial_probe,
.priv_auto = sizeof(struct sti_asc_serial),
};
-
.flags = DM_FLAG_PRE_RELOC,
#endif
};
-
.probe = stm32_timer_probe,
.ops = &stm32_timer_ops,
};
-
U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table);
#endif /* CONFIG_DM_ETH */
-
#define DBG(stuff...) debug("udc: " stuff)
#endif
-
/* Dealloc all events */
unbind_all_ports();
}
-
setup.dom = DOMID_SELF;
setup.nr_frames = 0;
}
-
#define CONFIG_SYS_CS1_CTRL 0x0100
#endif /* __AMCORE_CONFIG_H */
-
#endif /* CONFIG_SPL_BUILD */
#endif /* __CONFIG_CM_T335_H */
-
#include <configs/bmips_bcm6318.h>
#define CONFIG_REMAKE_ELF
-
#include <configs/bmips_bcm6328.h>
#define CONFIG_REMAKE_ELF
-
#include <configs/bmips_bcm6348.h>
#define CONFIG_REMAKE_ELF
-
#include <configs/bmips_bcm6368.h>
#define CONFIG_REMAKE_ELF
-
"emsdp rom lock\0"
#endif /* _CONFIG_EMSDP_H_ */
-
#include <configs/bmips_bcm6358.h>
#define CONFIG_REMAKE_ELF
-
#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
/* EEprom support */
-
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_KIRKWOOD_GPIO
#endif /* _CONFIG_NAS220_H */
-
#include <configs/bmips_common.h>
#include <configs/bmips_bcm3380.h>
-
#include <configs/bmips_bcm6362.h>
#define CONFIG_REMAKE_ELF
-
#include <configs/bmips_common.h>
#include <configs/bmips_bcm6338.h>
-
#include <configs/bmips_bcm6358.h>
#define CONFIG_REMAKE_ELF
-
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif /*_VERDIN_IMX8MM_H */
-
};
#endif /* __spi_coldfire_h */
-
#define CLK_SGMII_CDR_FB 3
#endif /* _DT_BINDINGS_CLK_MT7622_H */
-
#define UTMI_PHY_INVALID 0xff
#endif /* _COMPHY_DATA_H_ */
-
#define A_DELAY_PS(val) ((val) & 0xffff)
#define G_DELAY_PS(val) ((val) & 0xffff)
#endif
-
#define OMAP4_UART4_RX 0x11c
#endif
-
#define STM32MP_PKG_AD 0x8
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
-
#define THERMAL_NO_LIMIT (~0)
#endif
-
#else
#define NANDARGS ""
#endif
-
#define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
#endif /* _LINUX_SERIAL_REG_H */
-
int smem_get_free_space(struct udevice *dev, unsigned int host);
#endif /* _smem_h_ */
-
0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
0xe1, 0x00, 0x00, 0x01
};
-
memset(net_server_ethaddr, 0, 6);
}
#endif /* CONFIG_CMD_TFTPSRV */
-
write_tree_source_node(f, dti->dt, 0);
}
-
}
DM_TEST(dm_test_pci_ep_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
-
return 0;
}
DM_TEST(dm_test_smem_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
-
projects / uboot.git / commitdiff