feat(el3-runtime): handle traps for IMPDEF registers accesses

This patch introduces support to handle traps from lower ELs for
IMPDEF system register accesses. The actual support is left to the
platforms to implement.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I623d5c432b4ce4328b68f238c15b1c83df97c1e5

diff --git a/Makefile b/Makefile
index 98e448faba8f954812b12641153a403de13be5a5..d472054ed5e684ed7cb96c6b6ee75be9194a5453 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1204,6 +1204,7 @@ $(eval $(call assert_numerics,\
         TWED_DELAY \
         ENABLE_FEAT_TWED \
         SVE_VECTOR_LEN \
+       IMPDEF_SYSREG_TRAP \
 )))
 
 ifdef KEY_SIZE
@@ -1333,6 +1334,7 @@ $(eval $(call add_defines,\
         TWED_DELAY \
         ENABLE_FEAT_TWED \
        CONDITIONAL_CMO \
+       IMPDEF_SYSREG_TRAP \
 )))
 
 ifeq (${SANITIZE_UB},trap)

diff --git a/bl31/bl31_traps.c b/bl31/bl31_traps.c
index b12185ddc36c361dff56e8301e39668f13d4b539..2cfe14a833894c06686ff005a7b517791a5ae86a 100644 (file)
--- a/bl31/bl31_traps.c
+++ b/bl31/bl31_traps.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -11,13 +12,19 @@
 
 int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx)
 {
-       switch (esr_el3 & ISS_SYSREG_OPCODE_MASK) {
+       uint64_t __unused opcode = esr_el3 & ISS_SYSREG_OPCODE_MASK;
+
 #if ENABLE_FEAT_RNG_TRAP
-       case ISS_SYSREG_OPCODE_RNDR:
-       case ISS_SYSREG_OPCODE_RNDRRS:
+       if ((opcode == ISS_SYSREG_OPCODE_RNDR) || (opcode == ISS_SYSREG_OPCODE_RNDRRS)) {
                return plat_handle_rng_trap(esr_el3, ctx);
+       }
 #endif
-       default:
-               return TRAP_RET_UNHANDLED;
+
+#if IMPDEF_SYSREG_TRAP
+       if ((opcode & ISS_SYSREG_OPCODE_IMPDEF) == ISS_SYSREG_OPCODE_IMPDEF) {
+               return plat_handle_impdef_trap(esr_el3, ctx);
        }
+#endif
+
+       return TRAP_RET_UNHANDLED;
 }

diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 03be7862e32daf7286e4ccc96f97a86a86374616..818fd0baff1353f17c61bdbaa6300500d80555a8 100644 (file)
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -627,6 +627,10 @@ Common build options
    translation library (xlat tables v2) must be used; version 1 of translation
    library is not supported.
 
+-  ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for
+   implementation defined system register accesses from lower ELs. Default
+   value is ``0``.
+
 -  ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the
    bottom, higher addresses at the top. This build flag can be set to '1' to
    invert this behavior. Lower addresses will be printed at the top and higher

diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index bc9c00f3c569a4cfdf331f0eed92a0eae105a2c5..06191191b284d23aa2040f5c8ddf2fb6da750fc3 100644 (file)
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -3530,6 +3530,38 @@ The return value indicates how to proceed:
 
 This function needs to be implemented by a platform if it enables FEAT_RNG_TRAP.
 
+Function : plat_handle_impdef_trap
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+    Argument : uint64_t
+    Argument : cpu_context_t *
+    Return   : int
+
+This function is invoked by BL31's exception handler when there is a synchronous
+system register trap caused by access to the implementation defined registers.
+It allows platforms enabling ``IMPDEF_SYSREG_TRAP`` to emulate those system
+registers choosing to program bits of their choice.
+
+The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3
+syndrome register, which encodes the instruction that was trapped.
+
+The second parameter (``cpu_context_t *ctx``) represents the CPU state in the
+lower exception level, at the time when the execution of the ``mrs`` instruction
+was trapped.
+
+The return value indicates how to proceed:
+
+-  When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic.
+-  When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return
+   to the same instruction, so its execution will be repeated.
+-  When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return
+   to the next instruction.
+
+This function needs to be implemented by a platform if it enables
+IMPDEF_SYSREG_TRAP.
+
 Build flags
 -----------
 

diff --git a/include/bl31/sync_handle.h b/include/bl31/sync_handle.h
index e211575a6ab2c3eb92da68ecc3ef9fc1f57d8fe6..1ac4f98c7d678cea080ce0b12d5160688a604124 100644 (file)
--- a/include/bl31/sync_handle.h
+++ b/include/bl31/sync_handle.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,6 +17,7 @@
 #define ISS_SYSREG_DIRECTION_MASK      0x000001UL
 
 #define ISS_SYSREG_OPCODE_RNDR         0x30c808U
+#define ISS_SYSREG_OPCODE_IMPDEF       0x303c00U
 #define ISS_SYSREG_OPCODE_RNDRRS       0x32c808U
 
 #define TRAP_RET_UNHANDLED             -1
@@ -54,6 +56,7 @@ static inline bool is_sysreg_iss_write(uint64_t esr)
 int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx);
 
 /* Prototypes for system register emulation handlers provided by platforms. */
+int plat_handle_impdef_trap(uint64_t esr_el3, cpu_context_t *ctx);
 int plat_handle_rng_trap(uint64_t esr_el3, cpu_context_t *ctx);
 
 #endif /* __ASSEMBLER__ */

diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 808a058b2e646fad0c1b20efb4a4e8dd7bb794aa..a7bc426c2697d692582522324d22dd2683b6c95b 100644 (file)
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -240,6 +240,9 @@ HASH_ALG                    := sha256
 # operations.
 HW_ASSISTED_COHERENCY          := 0
 
+# Flag to enable trapping of implementation defined sytem registers
+IMPDEF_SYSREG_TRAP             := 0
+
 # Set the default algorithm for the generation of Trusted Board Boot keys
 KEY_ALG                                := rsa