]> git.baikalelectronics.ru Git - kernel.git/commitdiff
drm/i915/gt: Allocate i915_fence_reg array
authorChris Wilson <chris@chris-wilson.co.uk>
Mon, 16 Mar 2020 11:38:46 +0000 (11:38 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Mon, 16 Mar 2020 20:28:29 +0000 (20:28 +0000)
Since the number of fence regs can vary dramactically between platforms,
allocate the array on demand so we don't waste as much space.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200316113846.4974-4-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/gt/intel_ggtt.c
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
drivers/gpu/drm/i915/gt/intel_gtt.h
drivers/gpu/drm/i915/i915_vma.h

index bde4f64a41f7e042a9c8f9e00c383d5b0d480d35..8fcf14372d7a7d2579e09c637ed8394f87679d01 100644 (file)
@@ -698,11 +698,13 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
  */
 void i915_ggtt_driver_release(struct drm_i915_private *i915)
 {
+       struct i915_ggtt *ggtt = &i915->ggtt;
        struct pagevec *pvec;
 
-       fini_aliasing_ppgtt(&i915->ggtt);
+       fini_aliasing_ppgtt(ggtt);
 
-       ggtt_cleanup_hw(&i915->ggtt);
+       intel_ggtt_fini_fences(ggtt);
+       ggtt_cleanup_hw(ggtt);
 
        pvec = &i915->mm.wc_stash.pvec;
        if (pvec->nr) {
index 94af75673a588fe60d6438ef2ffc520478a136eb..b6ba68c425462ddfb47f625ed3c1d7f11ade4d60 100644 (file)
@@ -857,6 +857,11 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
        if (intel_vgpu_active(i915))
                num_fences = intel_uncore_read(uncore,
                                               vgtif_reg(avail_rs.fence_num));
+       ggtt->fence_regs = kcalloc(num_fences,
+                                  sizeof(*ggtt->fence_regs),
+                                  GFP_KERNEL);
+       if (!ggtt->fence_regs)
+               num_fences = 0;
 
        /* Initialize fence registers to zero */
        for (i = 0; i < num_fences; i++) {
@@ -871,6 +876,11 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
        intel_ggtt_restore_fences(ggtt);
 }
 
+void intel_ggtt_fini_fences(struct i915_ggtt *ggtt)
+{
+       kfree(ggtt->fence_regs);
+}
+
 void intel_gt_init_swizzling(struct intel_gt *gt)
 {
        struct drm_i915_private *i915 = gt->i915;
index 3b3eb5bf1b75aaefcf8759c3852ed760f6cc4a79..9850f6a85d2aca0b4e5fd2086aea9ce02f5e7fba 100644 (file)
@@ -64,6 +64,7 @@ void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
                                         struct sg_table *pages);
 
 void intel_ggtt_init_fences(struct i915_ggtt *ggtt);
+void intel_ggtt_fini_fences(struct i915_ggtt *ggtt);
 
 void intel_gt_init_swizzling(struct intel_gt *gt);
 
index ce6ff9d3a35073f77d621f0f86cca44087d01f9a..d93ebdf3fa0ef81d986520ce2d8a5de6db2ba3bd 100644 (file)
@@ -26,7 +26,6 @@
 #include <drm/drm_mm.h>
 
 #include "gt/intel_reset.h"
-#include "gt/intel_ggtt_fencing.h"
 #include "i915_selftest.h"
 #include "i915_vma_types.h"
 
@@ -135,6 +134,8 @@ typedef u64 gen8_pte_t;
 #define GEN8_PDE_IPS_64K BIT(11)
 #define GEN8_PDE_PS_2M   BIT(7)
 
+struct i915_fence_reg;
+
 #define for_each_sgt_daddr(__dp, __iter, __sgt) \
        __for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE)
 
@@ -333,7 +334,7 @@ struct i915_ggtt {
        u32 pin_bias;
 
        unsigned int num_fences;
-       struct i915_fence_reg fence_regs[I915_MAX_NUM_FENCES];
+       struct i915_fence_reg *fence_regs;
        struct list_head fence_list;
 
        /**
index 2764c277326f4eecdcb35e576b392fd8b51d8c62..b958ad07f212941ebd67e6e13bbaa19327c081ca 100644 (file)
@@ -30,6 +30,7 @@
 
 #include <drm/drm_mm.h>
 
+#include "gt/intel_ggtt_fencing.h"
 #include "gem/i915_gem_object.h"
 
 #include "i915_gem_gtt.h"