cadence: Change logic in uart driver

Write char if fifo is empty. If this is done like this all chars are
printed. Because origin code just put that chars to fifo and in case of
reset messages were missing.

Before this change chars are put to fifo and only check before adding if
fifo is full. The patch is changing this logic that it is adding char only
when fifo is empty to make sure that in case of reset (by another SW for
example) all chars are printed. Maybe one char can be missed but for IP
itself it is much easier to send just one char compare to full fifo.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Ic24c2c1252bce24be2aed68ee29477ca4a549e5f

diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S
index d1995e3e68bec9627d6080cdce90f5e5e45c326f..4c1a80efc672891233ca1b2667dbabbf38d70681 100644 (file)
--- a/drivers/cadence/uart/aarch64/cdns_console.S
+++ b/drivers/cadence/uart/aarch64/cdns_console.S
@@ -105,15 +105,15 @@ func console_cdns_core_putc
        cmp     w0, #0xA
        b.ne    2f
 1:
-       /* Check if the transmit FIFO is full */
+       /* Check if the transmit FIFO is empty */
        ldr     w2, [x1, #R_UART_SR]
-       tbnz    w2, #UART_SR_INTR_TFUL_BIT, 1b
+       tbz     w2, #UART_SR_INTR_TEMPTY_BIT, 1b
        mov     w2, #0xD
        str     w2, [x1, #R_UART_TX]
 2:
-       /* Check if the transmit FIFO is full */
+       /* Check if the transmit FIFO is empty */
        ldr     w2, [x1, #R_UART_SR]
-       tbnz    w2, #UART_SR_INTR_TFUL_BIT, 2b
+       tbz     w2, #UART_SR_INTR_TEMPTY_BIT, 2b
        str     w0, [x1, #R_UART_TX]
        ret
 endfunc console_cdns_core_putc

diff --git a/include/drivers/cadence/cdns_uart.h b/include/drivers/cadence/cdns_uart.h
index 46ba4663eda9c00e06a365a289126628e61dfab0..30ca910b923774c2c54b9d1da0789ba26b796323 100644 (file)
--- a/include/drivers/cadence/cdns_uart.h
+++ b/include/drivers/cadence/cdns_uart.h
@@ -21,6 +21,7 @@
 #define R_UART_SR              0x2C
 #define UART_SR_INTR_REMPTY_BIT        1
 #define UART_SR_INTR_TFUL_BIT  4
+#define UART_SR_INTR_TEMPTY_BIT        3
 
 #define R_UART_TX      0x30
 #define R_UART_RX      0x30