drm/i915: Kill duplicated cdclk readout code from i2c

We have a slightly different way of readoing out the cdclk in
gmbus_set_freq(). Kill that and just call .get_display_clock_speed().

Also need to remove the GMBUSFREQ update from intel_i2c_reset() since
that gets called way too early. Let's do it in intel_modeset_init_hw()
instead, and also pull the initial vlv_cdclk_freq update there from
init_clock gating.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ac3ee2cee4b6034c75c070750c05779d1d16c62f..5155811768c5b5f96932d4a1d6e36a0fb99b7424 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4466,7 +4466,7 @@ static void modeset_update_crtc_power_domains(struct drm_device *dev)
 }
 
 /* returns HPLL frequency in kHz */
-int valleyview_get_vco(struct drm_i915_private *dev_priv)
+static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 {
        int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 
@@ -4479,6 +4479,22 @@ int valleyview_get_vco(struct drm_i915_private *dev_priv)
        return vco_freq[hpll_freq] * 1000;
 }
 
+static void vlv_update_cdclk(struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+
+       dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
+       DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
+                        dev_priv->vlv_cdclk_freq);
+
+       /*
+        * Program the gmbus_freq based on the cdclk frequency.
+        * BSpec erroneously claims we should aim for 4MHz, but
+        * in fact 1MHz is the correct frequency.
+        */
+       I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
+}
+
 /* Adjust CDclk dividers to allow high res or save power if possible */
 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
 {
@@ -4486,7 +4502,6 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
        u32 val, cmd;
 
        WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
-       dev_priv->vlv_cdclk_freq = cdclk;
 
        if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
                cmd = 2;
@@ -4543,8 +4558,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
        vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
        mutex_unlock(&dev_priv->dpio_lock);
 
-       /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
-       intel_i2c_reset(dev);
+       vlv_update_cdclk(dev);
 }
 
 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
@@ -12440,6 +12454,9 @@ void intel_modeset_init_hw(struct drm_device *dev)
 {
        intel_prepare_ddi(dev);
 
+       if (IS_VALLEYVIEW(dev))
+               vlv_update_cdclk(dev);
+
        intel_init_clock_gating(dev);
 
        intel_reset_dpio(dev);

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 056fca96b141d456fd65c21d3945a8fb1c5a77af..4d4f735a8ad937b14f61da1d2353358ac4ff4865 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -830,7 +830,6 @@ void hsw_disable_ips(struct intel_crtc *crtc);
 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
 enum intel_display_power_domain
 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
-int valleyview_get_vco(struct drm_i915_private *dev_priv);
 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
                                 struct intel_crtc_config *pipe_config);
 int intel_format_to_fourcc(int format);

diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 9ce4f0945f979fa394e08fdde39fb6481ffeaad3..b31088a551f20ffc376d5e65a14d257164ec1afe 100644 (file)
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -34,11 +34,6 @@
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
 
-enum disp_clk {
-       CDCLK,
-       CZCLK
-};
-
 struct gmbus_port {
        const char *name;
        int reg;
@@ -63,60 +58,11 @@ to_intel_gmbus(struct i2c_adapter *i2c)
        return container_of(i2c, struct intel_gmbus, adapter);
 }
 
-static int get_disp_clk_div(struct drm_i915_private *dev_priv,
-                           enum disp_clk clk)
-{
-       u32 reg_val;
-       int clk_ratio;
-
-       reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO);
-
-       if (clk == CDCLK)
-               clk_ratio =
-                       ((reg_val & CDCLK_FREQ_MASK) >> CDCLK_FREQ_SHIFT) + 1;
-       else
-               clk_ratio = (reg_val & CZCLK_FREQ_MASK) + 1;
-
-       return clk_ratio;
-}
-
-static void gmbus_set_freq(struct drm_i915_private *dev_priv)
-{
-       int vco, gmbus_freq = 0, cdclk_div;
-
-       BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
-
-       vco = valleyview_get_vco(dev_priv) / 1000;
-
-       /* Get the CDCLK divide ratio */
-       cdclk_div = get_disp_clk_div(dev_priv, CDCLK);
-
-       /*
-        * Program the gmbus_freq based on the cdclk frequency.
-        * BSpec erroneously claims we should aim for 4MHz, but
-        * in fact 1MHz is the correct frequency.
-        */
-       if (cdclk_div)
-               gmbus_freq = (vco << 1) / cdclk_div;
-
-       if (WARN_ON(gmbus_freq == 0))
-               return;
-
-       I915_WRITE(GMBUSFREQ_VLV, gmbus_freq);
-}
-
 void
 intel_i2c_reset(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
 
-       /*
-        * In BIOS-less system, program the correct gmbus frequency
-        * before reading edid.
-        */
-       if (IS_VALLEYVIEW(dev))
-               gmbus_set_freq(dev_priv);
-
        I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
        I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
 }

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 146101c9476949cd6cf588f5079cde0647d919e7..719db7105614917152241385c753c984d868e483 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5595,10 +5595,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
        }
        DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
 
-       dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-       DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
-                        dev_priv->vlv_cdclk_freq);
-
        I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 
        /* WaDisableEarlyCull:vlv */