arm: Remove flea3 board

This board has not been converted to CONFIG_DM by the deadline.
Remove it.  As this is the last mx35 platform, remove that support as
well.

Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 79e29ee3cf89cee111e840105c128b7af98f2a4e..1b1767d7ba4746f0d492cc5617565f61aa732e03 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -605,11 +605,6 @@ config TARGET_STV0991
        select SPI_FLASH
        imply CMD_DM
 
-config TARGET_FLEA3
-       bool "Support flea3"
-       select CPU_ARM1136
-       select GPIO_EXTRA_HEADER
-
 config ARCH_BCM283X
        bool "Broadcom BCM283X family"
        select DM
@@ -2149,7 +2144,6 @@ source "board/armltd/total_compute/Kconfig"
 
 source "board/bosch/shc/Kconfig"
 source "board/bosch/guardian/Kconfig"
-source "board/CarMediaLab/flea3/Kconfig"
 source "board/Marvell/aspenite/Kconfig"
 source "board/Marvell/octeontx/Kconfig"
 source "board/Marvell/octeontx2/Kconfig"

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ce977bf6323f1b8fe4f993101a725118029ebe8c..6c9a00c5a481e01e80765ce9897966c655e029c5 100644 (file)
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -111,7 +111,7 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
 libs-y += arch/arm/mach-imx/
 endif
 else

diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile
index 24c33861cbfa9dac39ba739eb6d68ddba9b8ed3b..68d686a5dc775b90d73ab0d1fbe24c23f0cc0e6c 100644 (file)
--- a/arch/arm/cpu/arm1136/Makefile
+++ b/arch/arm/cpu/arm1136/Makefile
@@ -7,4 +7,3 @@ extra-y = start.o
 
 obj-y += ../arm11/
 obj-$(CONFIG_MX31) += mx31/
-obj-$(CONFIG_MX35) += mx35/

diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile
deleted file mode 100644 (file)
index 36568f9..0000000
--- a/arch/arm/cpu/arm1136/mx35/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-
-obj-y  += generic.o
-obj-y  += timer.o
-obj-y  += mx35_sdram.o
-obj-y  += relocate.o

diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
deleted file mode 100644 (file)
index cbf76ab..0000000
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ /dev/null
@@ -1,530 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <command.h>
-#include <div64.h>
-#include <init.h>
-#include <net.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#ifdef CONFIG_FSL_ESDHC_IMX
-#include <fsl_esdhc_imx.h>
-#endif
-#include <netdev.h>
-#include <spl.h>
-
-#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
-#define CLK_CODE_ARM(c)                (((c) >> 16) & 0xFF)
-#define CLK_CODE_AHB(c)                (((c) >>  8) & 0xFF)
-#define CLK_CODE_PATH(c)       ((c) & 0xFF)
-
-#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-static int g_clk_mux_auto[8] = {
-       CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
-       CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
-};
-
-static int g_clk_mux_consumer[16] = {
-       CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
-       -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
-       CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
-       -1, -1, CLK_CODE(4, 2, 0), -1,
-};
-
-static int hsp_div_table[3][16] = {
-       {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
-       {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
-       {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
-};
-
-u32 get_cpu_rev(void)
-{
-       int reg;
-       struct iim_regs *iim =
-               (struct iim_regs *)IIM_BASE_ADDR;
-       reg = readl(&iim->iim_srev);
-       if (!reg) {
-               reg = readw(ROMPATCH_REV);
-               reg <<= 4;
-       } else {
-               reg += CHIP_REV_1_0;
-       }
-
-       return 0x35000 + (reg & 0xFF);
-}
-
-static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
-{
-       int *pclk_mux;
-       if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
-               pclk_mux = g_clk_mux_consumer +
-                       ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
-                       MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
-       } else {
-               pclk_mux = g_clk_mux_auto +
-                       ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
-                       MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
-       }
-
-       if ((*pclk_mux) == -1)
-               return -1;
-
-       if (fi && fd) {
-               if (!CLK_CODE_PATH(*pclk_mux)) {
-                       *fi = *fd = 1;
-                       return CLK_CODE_ARM(*pclk_mux);
-               }
-               if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
-                       *fi = 3;
-                       *fd = 4;
-               } else {
-                       *fi = 2;
-                       *fd = 3;
-               }
-       }
-       return CLK_CODE_ARM(*pclk_mux);
-}
-
-static int get_ahb_div(u32 pdr0)
-{
-       int *pclk_mux;
-
-       pclk_mux = g_clk_mux_consumer +
-               ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
-               MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
-
-       if ((*pclk_mux) == -1)
-               return -1;
-
-       return CLK_CODE_AHB(*pclk_mux);
-}
-
-static u32 decode_pll(u32 reg, u32 infreq)
-{
-       u32 mfi = (reg >> 10) & 0xf;
-       s32 mfn = reg & 0x3ff;
-       u32 mfd = (reg >> 16) & 0x3ff;
-       u32 pd = (reg >> 26) & 0xf;
-
-       mfi = mfi <= 5 ? 5 : mfi;
-       mfn = mfn >= 512 ? mfn - 1024 : mfn;
-       mfd += 1;
-       pd += 1;
-
-       return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
-               mfd * pd);
-}
-
-static u32 get_mcu_main_clk(void)
-{
-       u32 arm_div = 0, fi = 0, fd = 0;
-       struct ccm_regs *ccm =
-               (struct ccm_regs *)IMX_CCM_BASE;
-       arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
-       fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
-       return fi / (arm_div * fd);
-}
-
-static u32 get_ipg_clk(void)
-{
-       u32 freq = get_mcu_main_clk();
-       struct ccm_regs *ccm =
-               (struct ccm_regs *)IMX_CCM_BASE;
-       u32 pdr0 = readl(&ccm->pdr0);
-
-       return freq / (get_ahb_div(pdr0) * 2);
-}
-
-static u32 get_ipg_per_clk(void)
-{
-       u32 freq = get_mcu_main_clk();
-       struct ccm_regs *ccm =
-               (struct ccm_regs *)IMX_CCM_BASE;
-       u32 pdr0 = readl(&ccm->pdr0);
-       u32 pdr4 = readl(&ccm->pdr4);
-       u32 div;
-       if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
-               div = CCM_GET_DIVIDER(pdr4,
-                       MXC_CCM_PDR4_PER0_PODF_MASK,
-                       MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
-       } else {
-               div = CCM_GET_DIVIDER(pdr0,
-                       MXC_CCM_PDR0_PER_PODF_MASK,
-                       MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
-               div *= get_ahb_div(pdr0);
-       }
-       return freq / div;
-}
-
-u32 imx_get_uartclk(void)
-{
-       u32 freq;
-       struct ccm_regs *ccm =
-               (struct ccm_regs *)IMX_CCM_BASE;
-       u32 pdr4 = readl(&ccm->pdr4);
-
-       if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
-               freq = get_mcu_main_clk();
-       else
-               freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
-       freq /= CCM_GET_DIVIDER(pdr4,
-                       MXC_CCM_PDR4_UART_PODF_MASK,
-                       MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
-       return freq;
-}
-
-unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
-{
-       u32 nfc_pdf, hsp_podf;
-       u32 pll, ret_val = 0, usb_podf;
-       struct ccm_regs *ccm =
-               (struct ccm_regs *)IMX_CCM_BASE;
-
-       u32 reg = readl(&ccm->pdr0);
-       u32 reg4 = readl(&ccm->pdr4);
-
-       reg |= 0x1;
-
-       switch (clk) {
-       case CPU_CLK:
-               ret_val = get_mcu_main_clk();
-               break;
-       case AHB_CLK:
-               ret_val = get_mcu_main_clk();
-               break;
-       case HSP_CLK:
-               if (reg & CLKMODE_CONSUMER) {
-                       hsp_podf = (reg >> 20) & 0x3;
-                       pll = get_mcu_main_clk();
-                       hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
-                       if (hsp_podf > 0) {
-                               ret_val = pll / hsp_podf;
-                       } else {
-                               puts("mismatch HSP with ARM clock setting\n");
-                               ret_val = 0;
-                       }
-               } else {
-                       ret_val = get_mcu_main_clk();
-               }
-               break;
-       case IPG_CLK:
-               ret_val = get_ipg_clk();
-               break;
-       case IPG_PER_CLK:
-               ret_val = get_ipg_per_clk();
-               break;
-       case NFC_CLK:
-               nfc_pdf = (reg4 >> 28) & 0xF;
-               pll = get_mcu_main_clk();
-               /* AHB/nfc_pdf */
-               ret_val = pll / (nfc_pdf + 1);
-               break;
-       case USB_CLK:
-               usb_podf = (reg4 >> 22) & 0x3F;
-               if (reg4 & 0x200)
-                       pll = get_mcu_main_clk();
-               else
-                       pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
-
-               ret_val = pll / (usb_podf + 1);
-               break;
-       default:
-               printf("Unknown clock: %d\n", clk);
-               break;
-       }
-
-       return ret_val;
-}
-unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
-{
-       u32 ret_val = 0, pdf, pre_pdf, clk_sel;
-       struct ccm_regs *ccm =
-               (struct ccm_regs *)IMX_CCM_BASE;
-       u32 mpdr2 = readl(&ccm->pdr2);
-       u32 mpdr3 = readl(&ccm->pdr3);
-       u32 mpdr4 = readl(&ccm->pdr4);
-
-       switch (clk) {
-       case UART1_BAUD:
-       case UART2_BAUD:
-       case UART3_BAUD:
-               clk_sel = mpdr3 & (1 << 14);
-               pdf = (mpdr4 >> 10) & 0x3F;
-               ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
-               break;
-       case SSI1_BAUD:
-               pre_pdf = (mpdr2 >> 24) & 0x7;
-               pdf = mpdr2 & 0x3F;
-               clk_sel = mpdr2 & (1 << 6);
-               ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
-                               ((pre_pdf + 1) * (pdf + 1));
-               break;
-       case SSI2_BAUD:
-               pre_pdf = (mpdr2 >> 27) & 0x7;
-               pdf = (mpdr2 >> 8) & 0x3F;
-               clk_sel = mpdr2 & (1 << 6);
-               ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
-                               ((pre_pdf + 1) * (pdf + 1));
-               break;
-       case CSI_BAUD:
-               clk_sel = mpdr2 & (1 << 7);
-               pdf = (mpdr2 >> 16) & 0x3F;
-               ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
-               break;
-       case MSHC_CLK:
-               pre_pdf = readl(&ccm->pdr1);
-               clk_sel = (pre_pdf & 0x80);
-               pdf = (pre_pdf >> 22) & 0x3F;
-               pre_pdf = (pre_pdf >> 28) & 0x7;
-               ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
-                               ((pre_pdf + 1) * (pdf + 1));
-               break;
-       case ESDHC1_CLK:
-               clk_sel = mpdr3 & 0x40;
-               pdf = mpdr3 & 0x3F;
-               ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
-               break;
-       case ESDHC2_CLK:
-               clk_sel = mpdr3 & 0x40;
-               pdf = (mpdr3 >> 8) & 0x3F;
-               ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
-               break;
-       case ESDHC3_CLK:
-               clk_sel = mpdr3 & 0x40;
-               pdf = (mpdr3 >> 16) & 0x3F;
-               ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
-               break;
-       case SPDIF_CLK:
-               clk_sel = mpdr3 & 0x400000;
-               pre_pdf = (mpdr3 >> 29) & 0x7;
-               pdf = (mpdr3 >> 23) & 0x3F;
-               ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
-                               ((pre_pdf + 1) * (pdf + 1));
-               break;
-       default:
-               printf("%s(): This clock: %d not supported yet\n",
-                               __func__, clk);
-               break;
-       }
-
-       return ret_val;
-}
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
-       switch (clk) {
-       case MXC_ARM_CLK:
-               return get_mcu_main_clk();
-       case MXC_AHB_CLK:
-               break;
-       case MXC_IPG_CLK:
-               return get_ipg_clk();
-       case MXC_IPG_PERCLK:
-       case MXC_I2C_CLK:
-               return get_ipg_per_clk();
-       case MXC_UART_CLK:
-               return imx_get_uartclk();
-       case MXC_ESDHC1_CLK:
-               return mxc_get_peri_clock(ESDHC1_CLK);
-       case MXC_ESDHC2_CLK:
-               return mxc_get_peri_clock(ESDHC2_CLK);
-       case MXC_ESDHC3_CLK:
-               return mxc_get_peri_clock(ESDHC3_CLK);
-       case MXC_USB_CLK:
-               return mxc_get_main_clock(USB_CLK);
-       case MXC_FEC_CLK:
-               return get_ipg_clk();
-       case MXC_CSPI_CLK:
-               return get_ipg_clk();
-       }
-       return -1;
-}
-
-#ifdef CONFIG_FEC_MXC
-/*
- * The MX35 has no fuse for MAC, return a NULL MAC
- */
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
-       memset(mac, 0, 6);
-}
-
-u32 imx_get_fecclk(void)
-{
-       return mxc_get_clock(MXC_IPG_CLK);
-}
-#endif
-
-int do_mx35_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
-                      char *const argv[])
-{
-       u32 cpufreq = get_mcu_main_clk();
-       printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
-       printf("ipg clock     : %dHz\n", get_ipg_clk());
-       printf("ipg per clock : %dHz\n", get_ipg_per_clk());
-       printf("uart clock    : %dHz\n", mxc_get_clock(MXC_UART_CLK));
-
-       return 0;
-}
-
-U_BOOT_CMD(
-       clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
-       "display clocks",
-       ""
-);
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-static char *get_reset_cause(void)
-{
-       /* read RCSR register from CCM module */
-       struct ccm_regs *ccm =
-               (struct ccm_regs *)IMX_CCM_BASE;
-
-       u32 cause = readl(&ccm->rcsr) & 0x0F;
-
-       switch (cause) {
-       case 0x0000:
-               return "POR";
-       case 0x0002:
-               return "JTAG";
-       case 0x0004:
-               return "RST";
-       case 0x0008:
-               return "WDOG";
-       default:
-               return "unknown reset";
-       }
-}
-
-int print_cpuinfo(void)
-{
-       u32 srev = get_cpu_rev();
-
-       printf("CPU:   Freescale i.MX35 rev %d.%d at %d MHz.\n",
-               (srev & 0xF0) >> 4, (srev & 0x0F),
-               get_mcu_main_clk() / 1000000);
-
-       printf("Reset cause: %s\n", get_reset_cause());
-
-       return 0;
-}
-#endif
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(struct bd_info *bis)
-{
-       int rc = -ENODEV;
-
-#if defined(CONFIG_FEC_MXC)
-       rc = fecmxc_initialize(bis);
-#endif
-
-       return rc;
-}
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(struct bd_info *bis)
-{
-       return fsl_esdhc_mmc_init(bis);
-}
-#endif
-
-int get_clocks(void)
-{
-#ifdef CONFIG_FSL_ESDHC_IMX
-#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
-       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
-       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-#else
-       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
-#endif
-#endif
-       return 0;
-}
-
-#define RCSR_MEM_CTL_WEIM      0
-#define RCSR_MEM_CTL_NAND      1
-#define RCSR_MEM_CTL_ATA       2
-#define RCSR_MEM_CTL_EXPANSION 3
-#define RCSR_MEM_TYPE_NOR      0
-#define RCSR_MEM_TYPE_ONENAND  2
-#define RCSR_MEM_TYPE_SD       0
-#define RCSR_MEM_TYPE_I2C      2
-#define RCSR_MEM_TYPE_SPI      3
-
-u32 spl_boot_device(void)
-{
-       struct ccm_regs *ccm =
-               (struct ccm_regs *)IMX_CCM_BASE;
-
-       u32 rcsr = readl(&ccm->rcsr);
-       u32 mem_type, mem_ctl;
-
-       /* In external mode, no boot device is returned */
-       if ((rcsr >> 10) & 0x03)
-               return BOOT_DEVICE_NONE;
-
-       mem_ctl = (rcsr >> 25) & 0x03;
-       mem_type = (rcsr >> 23) & 0x03;
-
-       switch (mem_ctl) {
-       case RCSR_MEM_CTL_WEIM:
-               switch (mem_type) {
-               case RCSR_MEM_TYPE_NOR:
-                       return BOOT_DEVICE_NOR;
-               case RCSR_MEM_TYPE_ONENAND:
-                       return BOOT_DEVICE_ONENAND;
-               default:
-                       return BOOT_DEVICE_NONE;
-               }
-       case RCSR_MEM_CTL_NAND:
-               return BOOT_DEVICE_NAND;
-       case RCSR_MEM_CTL_EXPANSION:
-               switch (mem_type) {
-               case RCSR_MEM_TYPE_SD:
-                       return BOOT_DEVICE_MMC1;
-               case RCSR_MEM_TYPE_I2C:
-                       return BOOT_DEVICE_I2C;
-               case RCSR_MEM_TYPE_SPI:
-                       return BOOT_DEVICE_SPI;
-               default:
-                       return BOOT_DEVICE_NONE;
-               }
-       }
-
-       return BOOT_DEVICE_NONE;
-}

diff --git a/arch/arm/cpu/arm1136/mx35/mx35_sdram.c b/arch/arm/cpu/arm1136/mx35/mx35_sdram.c
deleted file mode 100644 (file)
index f120e84..0000000
--- a/arch/arm/cpu/arm1136/mx35/mx35_sdram.c
+++ /dev/null
@@ -1,120 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
- */
-
-#include <asm/io.h>
-#include <linux/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <linux/types.h>
-#include <asm/arch/sys_proto.h>
-
-#define ESDCTL_DDR2_EMR2       0x04000000
-#define ESDCTL_DDR2_EMR3       0x06000000
-#define ESDCTL_PRECHARGE       0x00000400
-#define ESDCTL_DDR2_EN_DLL     0x02000400
-#define ESDCTL_DDR2_RESET_DLL  0x00000333
-#define ESDCTL_DDR2_MR         0x00000233
-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
-
-enum {
-       SMODE_NORMAL =  0,
-       SMODE_PRECHARGE,
-       SMODE_AUTO_REFRESH,
-       SMODE_LOAD_REG,
-       SMODE_MANUAL_REFRESH
-};
-
-#define set_mode(x, en, m)     (x | (en << 31) | (m << 28))
-
-static inline void dram_wait(unsigned int count)
-{
-       volatile unsigned int wait = count;
-
-       while (wait--)
-               ;
-
-}
-
-void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
-       u32 row, u32 col, u32 dsize, u32 refresh)
-{
-       struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
-       u32 *cfg_reg, *ctl_reg;
-       u32 val;
-       u32 ctlval;
-
-       switch (start_address) {
-       case CSD0_BASE_ADDR:
-               cfg_reg = &esdc->esdcfg0;
-               ctl_reg = &esdc->esdctl0;
-               break;
-       case CSD1_BASE_ADDR:
-               cfg_reg = &esdc->esdcfg1;
-               ctl_reg = &esdc->esdctl1;
-               break;
-       default:
-               return;
-       }
-
-       /* The MX35 supports 11 up to 14 rows */
-       if (row < 11 || row > 14 || col < 8 || col > 10)
-               return;
-       ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
-
-       /* Initialize MISC register for DDR2 */
-       val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
-               ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
-       writel(val, &esdc->esdmisc);
-       val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
-       writel(val, &esdc->esdmisc);
-
-       /*
-        * according to DDR2 specs, wait a while before
-        * the PRECHARGE_ALL command
-        */
-       dram_wait(0x20000);
-
-       /* Load DDR2 config and timing */
-       writel(ddr2_config, cfg_reg);
-
-       /* Precharge ALL */
-       writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
-               ctl_reg);
-       writel(0xda, start_address + ESDCTL_PRECHARGE);
-
-       /* Load mode */
-       writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
-               ctl_reg);
-       writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
-       writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
-       writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-       writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
-
-       /* Precharge ALL */
-       writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
-               ctl_reg);
-       writel(0xda, start_address + ESDCTL_PRECHARGE);
-
-       /* Set mode auto refresh : at least two refresh are required */
-       writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
-               ctl_reg);
-       writel(0xda, start_address);
-       writel(0xda, start_address);
-
-       writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
-               ctl_reg);
-       writeb(0xda, start_address + ESDCTL_DDR2_MR);
-       writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
-
-       /* OCD mode exit */
-       writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-
-       /* Set normal mode */
-       writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
-               ctl_reg);
-
-       dram_wait(0x20000);
-
-       /* Do not set delay lines, only for MDDR */
-}

diff --git a/arch/arm/cpu/arm1136/mx35/relocate.S b/arch/arm/cpu/arm1136/mx35/relocate.S
deleted file mode 100644 (file)
index e41e5a5..0000000
--- a/arch/arm/cpu/arm1136/mx35/relocate.S
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  relocate - i.MX35-specific vector relocation
- *
- *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
- */
-
-#include <linux/linkage.h>
-
-/*
- * The i.MX35 SoC is very specific with respect to exceptions: it
- * does not provide RAM at the high vectors address (0xFFFF0000),
- * thus only the low address (0x00000000) is useable; but that is
- * in ROM, so let's avoid relocating the vectors.
- */
-       .section        .text.relocate_vectors,"ax",%progbits
-
-ENTRY(relocate_vectors)
-
-       bx      lr
-
-ENDPROC(relocate_vectors)

diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c
deleted file mode 100644 (file)
index f2541c3..0000000
--- a/arch/arm/cpu/arm1136/mx35/timer.c
+++ /dev/null
@@ -1,46 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/ptrace.h>
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR       (1<<15)        /* Software reset */
-#define GPTCR_FRR       (1<<9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32   (4<<6)    /* Clock source */
-#define GPTCR_TEN       (1)    /* Timer enable */
-
-/*
- * nothing really to do with interrupts, just starts up a counter.
- * The 32KHz 32-bit timer overruns in 134217 seconds
- */
-int timer_init(void)
-{
-       int i;
-       struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
-       struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
-
-       /* setup GP Timer 1 */
-       writel(GPTCR_SWR, &gpt->ctrl);
-
-       writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
-
-       for (i = 0; i < 100; i++)
-               writel(0, &gpt->ctrl); /* We have no udelay by now */
-       writel(0, &gpt->pre); /* prescaler = 1 */
-       /* Freerun Mode, 32KHz input */
-       writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
-                       &gpt->ctrl);
-       writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
-
-       return 0;
-}

diff --git a/arch/arm/include/asm/arch-mx35/clock.h b/arch/arm/include/asm/arch-mx35/clock.h
deleted file mode 100644 (file)
index cb0b53a..0000000
--- a/arch/arm/include/asm/arch-mx35/clock.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-#ifdef CONFIG_MX35_HCLK_FREQ
-#define MXC_HCLK       CONFIG_MX35_HCLK_FREQ
-#else
-#define MXC_HCLK       24000000
-#endif
-
-#ifdef CONFIG_MX35_CLK32
-#define MXC_CLK32      CONFIG_MX35_CLK32
-#else
-#define MXC_CLK32      32768
-#endif
-
-enum mxc_clock {
-       MXC_ARM_CLK,
-       MXC_AHB_CLK,
-       MXC_IPG_CLK,
-       MXC_IPG_PERCLK,
-       MXC_UART_CLK,
-       MXC_ESDHC1_CLK,
-       MXC_ESDHC2_CLK,
-       MXC_ESDHC3_CLK,
-       MXC_USB_CLK,
-       MXC_CSPI_CLK,
-       MXC_FEC_CLK,
-       MXC_I2C_CLK,
-};
-
-enum mxc_main_clock {
-       CPU_CLK,
-       AHB_CLK,
-       IPG_CLK,
-       IPG_PER_CLK,
-       NFC_CLK,
-       USB_CLK,
-       HSP_CLK,
-};
-
-enum mxc_peri_clock {
-       UART1_BAUD,
-       UART2_BAUD,
-       UART3_BAUD,
-       SSI1_BAUD,
-       SSI2_BAUD,
-       CSI_BAUD,
-       MSHC_CLK,
-       ESDHC1_CLK,
-       ESDHC2_CLK,
-       ESDHC3_CLK,
-       SPDIF_CLK,
-       SPI1_CLK,
-       SPI2_CLK,
-};
-
-u32 imx_get_uartclk(void);
-u32 imx_get_fecclk(void);
-unsigned int mxc_get_clock(enum mxc_clock clk);
-
-#endif /* __ASM_ARCH_CLOCK_H */

diff --git a/arch/arm/include/asm/arch-mx35/crm_regs.h b/arch/arm/include/asm/arch-mx35/crm_regs.h
deleted file mode 100644 (file)
index fc65a3a..0000000
--- a/arch/arm/include/asm/arch-mx35/crm_regs.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2004-2009 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__
-#define __CPU_ARM1136_MX35_CRM_REGS_H__
-
-/* Register bit definitions */
-#define MXC_CCM_CCMR_WFI                        (1 << 30)
-#define MXC_CCM_CCMR_STBY_EXIT_SRC              (1 << 29)
-#define MXC_CCM_CCMR_VSTBY                      (1 << 28)
-#define MXC_CCM_CCMR_WBEN                       (1 << 27)
-#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET        20
-#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK          (0xF << 20)
-#define MXC_CCM_CCMR_ROMW_OFFSET               18
-#define MXC_CCM_CCMR_ROMW_MASK                 (0x3 << 18)
-#define MXC_CCM_CCMR_RAMW_OFFSET               16
-#define MXC_CCM_CCMR_RAMW_MASK                 (0x3 << 16)
-#define MXC_CCM_CCMR_LPM_OFFSET                 14
-#define MXC_CCM_CCMR_LPM_MASK                   (0x3 << 14)
-#define MXC_CCM_CCMR_UPE                        (1 << 9)
-#define MXC_CCM_CCMR_MPE                        (1 << 3)
-
-#define MXC_CCM_PDR0_PER_SEL                   (1 << 26)
-#define MXC_CCM_PDR0_IPU_HND_BYP                (1 << 23)
-#define MXC_CCM_PDR0_HSP_PODF_OFFSET            20
-#define MXC_CCM_PDR0_HSP_PODF_MASK              (0x3 << 20)
-#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET                16
-#define MXC_CCM_PDR0_CON_MUX_DIV_MASK           (0xF << 16)
-#define MXC_CCM_PDR0_CKIL_SEL                  (1 << 15)
-#define MXC_CCM_PDR0_PER_PODF_OFFSET            12
-#define MXC_CCM_PDR0_PER_PODF_MASK              (0x7 << 12)
-#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET        9
-#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK          (0x7 << 9)
-#define MXC_CCM_PDR0_AUTO_CON                  0x1
-
-#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET           28
-#define MXC_CCM_PDR1_MSHC_PRDF_MASK             (0x7 << 28)
-#define MXC_CCM_PDR1_MSHC_PODF_OFFSET           22
-#define MXC_CCM_PDR1_MSHC_PODF_MASK             (0x3F << 22)
-#define MXC_CCM_PDR1_MSHC_M_U                  (1 << 7)
-
-#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET           27
-#define MXC_CCM_PDR2_SSI2_PRDF_MASK             (0x7 << 27)
-#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET           24
-#define MXC_CCM_PDR2_SSI1_PRDF_MASK             (0x7 << 24)
-#define MXC_CCM_PDR2_CSI_PODF_OFFSET            16
-#define MXC_CCM_PDR2_CSI_PODF_MASK              (0x3F << 16)
-#define MXC_CCM_PDR2_SSI2_PODF_OFFSET           8
-#define MXC_CCM_PDR2_SSI2_PODF_MASK             (0x3F << 8)
-#define MXC_CCM_PDR2_CSI_M_U                   (1 << 7)
-#define MXC_CCM_PDR2_SSI_M_U                   (1 << 6)
-#define MXC_CCM_PDR2_SSI1_PODF_OFFSET           0
-#define MXC_CCM_PDR2_SSI1_PODF_MASK             (0x3F)
-
-#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET          29
-#define MXC_CCM_PDR3_SPDIF_PRDF_MASK            (0x7 << 29)
-#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET          23
-#define MXC_CCM_PDR3_SPDIF_PODF_MASK            (0x3F << 23)
-#define MXC_CCM_PDR3_SPDIF_M_U                 (1 << 22)
-#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET         16
-#define MXC_CCM_PDR3_ESDHC3_PODF_MASK           (0x3F << 16)
-#define MXC_CCM_PDR3_UART_M_U                  (1 << 14)
-#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET         8
-#define MXC_CCM_PDR3_ESDHC2_PODF_MASK           (0x3F << 8)
-#define MXC_CCM_PDR3_ESDHC_M_U                 (1 << 6)
-#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET         0
-#define MXC_CCM_PDR3_ESDHC1_PODF_MASK           (0x3F)
-
-#define MXC_CCM_PDR4_NFC_PODF_OFFSET           28
-#define MXC_CCM_PDR4_NFC_PODF_MASK             (0xF << 28)
-#define MXC_CCM_PDR4_USB_PODF_OFFSET           22
-#define MXC_CCM_PDR4_USB_PODF_MASK             (0x3F << 22)
-#define MXC_CCM_PDR4_PER0_PODF_OFFSET          16
-#define MXC_CCM_PDR4_PER0_PODF_MASK            (0x3F << 16)
-#define MXC_CCM_PDR4_UART_PODF_OFFSET          10
-#define MXC_CCM_PDR4_UART_PODF_MASK            (0x3F << 10)
-#define MXC_CCM_PDR4_USB_M_U                   (1 << 9)
-
-/* Bit definitions for RCSR */
-#define MXC_CCM_RCSR_BUS_WIDTH                 (1 << 29)
-#define MXC_CCM_RCSR_BUS_16BIT                 (1 << 29)
-#define MXC_CCM_RCSR_PAGE_SIZE                 (3 << 27)
-#define MXC_CCM_RCSR_PAGE_512                  (0 << 27)
-#define MXC_CCM_RCSR_PAGE_2K                   (1 << 27)
-#define MXC_CCM_RCSR_PAGE_4K1                  (2 << 27)
-#define MXC_CCM_RCSR_PAGE_4K2                  (3 << 27)
-#define MXC_CCM_RCSR_SOFT_RESET                        (1 << 15)
-#define MXC_CCM_RCSR_NF16B                     (1 << 14)
-#define MXC_CCM_RCSR_NFC_4K                    (1 << 9)
-#define MXC_CCM_RCSR_NFC_FMS                   (1 << 8)
-
-/* Bit definitions for both MCU, PERIPHERAL PLL control registers */
-#define MXC_CCM_PCTL_BRM                        0x80000000
-#define MXC_CCM_PCTL_PD_OFFSET                  26
-#define MXC_CCM_PCTL_PD_MASK                    (0xF << 26)
-#define MXC_CCM_PCTL_MFD_OFFSET                 16
-#define MXC_CCM_PCTL_MFD_MASK                   (0x3FF << 16)
-#define MXC_CCM_PCTL_MFI_OFFSET                 10
-#define MXC_CCM_PCTL_MFI_MASK                   (0xF << 10)
-#define MXC_CCM_PCTL_MFN_OFFSET                 0
-#define MXC_CCM_PCTL_MFN_MASK                   0x3FF
-
-/* Bit definitions for Audio clock mux register*/
-#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET       12
-#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK         (0xF << 12)
-#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET      8
-#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK                (0xF << 8)
-#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET       4
-#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK         (0xF << 4)
-#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET       0
-#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK         (0xF << 0)
-
-/* Bit definitions for Clock gating Register*/
-#define MXC_CCM_CGR_CG_MASK                    0x3
-#define MXC_CCM_CGR_CG_OFF                     0x0
-#define MXC_CCM_CGR_CG_RUN_ON                  0x1
-#define MXC_CCM_CGR_CG_RUN_WAIT_ON             0x2
-#define MXC_CCM_CGR_CG_ON                      0x3
-
-#define MXC_CCM_CGR0_ASRC_OFFSET               0
-#define MXC_CCM_CGR0_ASRC_MASK                 (0x3 << 0)
-#define MXC_CCM_CGR0_ATA_OFFSET                        2
-#define MXC_CCM_CGR0_ATA_MASK                  (0x3 << 2)
-#define MXC_CCM_CGR0_CAN1_OFFSET               6
-#define MXC_CCM_CGR0_CAN1_MASK                 (0x3 << 6)
-#define MXC_CCM_CGR0_CAN2_OFFSET               8
-#define MXC_CCM_CGR0_CAN2_MASK                 (0x3 << 8)
-#define MXC_CCM_CGR0_CSPI1_OFFSET              10
-#define MXC_CCM_CGR0_CSPI1_MASK                        (0x3 << 10)
-#define MXC_CCM_CGR0_CSPI2_OFFSET              12
-#define MXC_CCM_CGR0_CSPI2_MASK                        (0x3 << 12)
-#define MXC_CCM_CGR0_ECT_OFFSET                        14
-#define MXC_CCM_CGR0_ECT_MASK                  (0x3 << 14)
-#define MXC_CCM_CGR0_EDIO_OFFSET               16
-#define MXC_CCM_CGR0_EDIO_MASK                 (0x3 << 16)
-#define MXC_CCM_CGR0_EMI_OFFSET                        18
-#define MXC_CCM_CGR0_EMI_MASK                  (0x3 << 18)
-#define MXC_CCM_CGR0_EPIT1_OFFSET              20
-#define MXC_CCM_CGR0_EPIT1_MASK                        (0x3 << 20)
-#define MXC_CCM_CGR0_EPIT2_OFFSET              22
-#define MXC_CCM_CGR0_EPIT2_MASK                        (0x3 << 22)
-#define MXC_CCM_CGR0_ESAI_OFFSET               24
-#define MXC_CCM_CGR0_ESAI_MASK                 (0x3 << 24)
-#define MXC_CCM_CGR0_ESDHC1_OFFSET             26
-#define MXC_CCM_CGR0_ESDHC1_MASK               (0x3 << 26)
-#define MXC_CCM_CGR0_ESDHC2_OFFSET             28
-#define MXC_CCM_CGR0_ESDHC2_MASK               (0x3 << 28)
-#define MXC_CCM_CGR0_ESDHC3_OFFSET             30
-#define MXC_CCM_CGR0_ESDHC3_MASK               (0x3 << 30)
-
-#define MXC_CCM_CGR1_FEC_OFFSET                        0
-#define MXC_CCM_CGR1_FEC_MASK                  (0x3 << 0)
-#define MXC_CCM_CGR1_GPIO1_OFFSET              2
-#define MXC_CCM_CGR1_GPIO1_MASK                        (0x3 << 2)
-#define MXC_CCM_CGR1_GPIO2_OFFSET              4
-#define MXC_CCM_CGR1_GPIO2_MASK                        (0x3 << 4)
-#define MXC_CCM_CGR1_GPIO3_OFFSET              6
-#define MXC_CCM_CGR1_GPIO3_MASK                        (0x3 << 6)
-#define MXC_CCM_CGR1_GPT_OFFSET                        8
-#define MXC_CCM_CGR1_GPT_MASK                  (0x3 << 8)
-#define MXC_CCM_CGR1_I2C1_OFFSET               10
-#define MXC_CCM_CGR1_I2C1_MASK                 (0x3 << 10)
-#define MXC_CCM_CGR1_I2C2_OFFSET               12
-#define MXC_CCM_CGR1_I2C2_MASK                 (0x3 << 12)
-#define MXC_CCM_CGR1_I2C3_OFFSET               14
-#define MXC_CCM_CGR1_I2C3_MASK                 (0x3 << 14)
-#define MXC_CCM_CGR1_IOMUXC_OFFSET             16
-#define MXC_CCM_CGR1_IOMUXC_MASK               (0x3 << 16)
-#define MXC_CCM_CGR1_IPU_OFFSET                        18
-#define MXC_CCM_CGR1_IPU_MASK                  (0x3 << 18)
-#define MXC_CCM_CGR1_KPP_OFFSET                        20
-#define MXC_CCM_CGR1_KPP_MASK                  (0x3 << 20)
-#define MXC_CCM_CGR1_MLB_OFFSET                        22
-#define MXC_CCM_CGR1_MLB_MASK                  (0x3 << 22)
-#define MXC_CCM_CGR1_MSHC_OFFSET               24
-#define MXC_CCM_CGR1_MSHC_MASK                 (0x3 << 24)
-#define MXC_CCM_CGR1_OWIRE_OFFSET              26
-#define MXC_CCM_CGR1_OWIRE_MASK                        (0x3 << 26)
-#define MXC_CCM_CGR1_PWM_OFFSET                        28
-#define MXC_CCM_CGR1_PWM_MASK                  (0x3 << 28)
-#define MXC_CCM_CGR1_RNGC_OFFSET               30
-#define MXC_CCM_CGR1_RNGC_MASK                 (0x3 << 30)
-
-#define MXC_CCM_CGR2_RTC_OFFSET                        0
-#define MXC_CCM_CGR2_RTC_MASK                  (0x3 << 0)
-#define MXC_CCM_CGR2_RTIC_OFFSET               2
-#define MXC_CCM_CGR2_RTIC_MASK                 (0x3 << 2)
-#define MXC_CCM_CGR2_SCC_OFFSET                        4
-#define MXC_CCM_CGR2_SCC_MASK                  (0x3 << 4)
-#define MXC_CCM_CGR2_SDMA_OFFSET               6
-#define MXC_CCM_CGR2_SDMA_MASK                 (0x3 << 6)
-#define MXC_CCM_CGR2_SPBA_OFFSET               8
-#define MXC_CCM_CGR2_SPBA_MASK                 (0x3 << 8)
-#define MXC_CCM_CGR2_SPDIF_OFFSET              10
-#define MXC_CCM_CGR2_SPDIF_MASK                        (0x3 << 10)
-#define MXC_CCM_CGR2_SSI1_OFFSET               12
-#define MXC_CCM_CGR2_SSI1_MASK                 (0x3 << 12)
-#define MXC_CCM_CGR2_SSI2_OFFSET               14
-#define MXC_CCM_CGR2_SSI2_MASK                 (0x3 << 14)
-#define MXC_CCM_CGR2_UART1_OFFSET              16
-#define MXC_CCM_CGR2_UART1_MASK                        (0x3 << 16)
-#define MXC_CCM_CGR2_UART2_OFFSET              18
-#define MXC_CCM_CGR2_UART2_MASK                        (0x3 << 18)
-#define MXC_CCM_CGR2_UART3_OFFSET              20
-#define MXC_CCM_CGR2_UART3_MASK                        (0x3 << 20)
-#define MXC_CCM_CGR2_USBOTG_OFFSET             22
-#define MXC_CCM_CGR2_USBOTG_MASK               (0x3 << 22)
-#define MXC_CCM_CGR2_WDOG_OFFSET               24
-#define MXC_CCM_CGR2_WDOG_MASK                 (0x3 << 24)
-#define MXC_CCM_CGR2_MAX_OFFSET                        26
-#define MXC_CCM_CGR2_MAX_MASK                  (0x3 << 26)
-#define MXC_CCM_CGR2_MAX_ENABLE                        (0x2 << 26)
-#define MXC_CCM_CGR2_AUDMUX_OFFSET             30
-#define MXC_CCM_CGR2_AUDMUX_MASK               (0x3 << 30)
-
-#define MXC_CCM_CGR3_CSI_OFFSET                        0
-#define MXC_CCM_CGR3_CSI_MASK                  (0x3 << 0)
-#define MXC_CCM_CGR3_IIM_OFFSET                        2
-#define MXC_CCM_CGR3_IIM_MASK                  (0x3 << 2)
-#define MXC_CCM_CGR3_GPU2D_OFFSET              4
-#define MXC_CCM_CGR3_GPU2D_MASK                        (0x3 << 4)
-
-#define MXC_CCM_COSR_CLKOSEL_MASK              0x1F
-#define MXC_CCM_COSR_CLKOSEL_OFFSET            0
-#define MXC_CCM_COSR_CLKOEN                    (1 << 5)
-#define MXC_CCM_COSR_CLKOUTDIV_1               (1 << 6)
-#define MXC_CCM_COSR_CLKOUT_DIV_MASK           (0x3F << 10)
-#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET         10
-#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK      (0x3 << 16)
-#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET    16
-#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK      (0x3 << 18)
-#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET    18
-#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK      (0x3 << 20)
-#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET    20
-#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK      (0x3 << 22)
-#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET    22
-#define MXC_CCM_COSR_ASRC_AUDIO_EN             (1 << 24)
-#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK      (0x3F << 26)
-#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET    26
-
-#endif

diff --git a/arch/arm/include/asm/arch-mx35/gpio.h b/arch/arm/include/asm/arch-mx35/gpio.h
deleted file mode 100644 (file)
index b3d3639..0000000
--- a/arch/arm/include/asm/arch-mx35/gpio.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
- */
-
-
-#ifndef __ASM_ARCH_MX35_GPIO_H
-#define __ASM_ARCH_MX35_GPIO_H
-
-#include <asm/mach-imx/gpio.h>
-
-#endif

diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h
deleted file mode 100644 (file)
index 3509004..0000000
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- */
-
-#ifndef __ASM_ARCH_MX35_H
-#define __ASM_ARCH_MX35_H
-
-#define ARCH_MXC
-
-/*
- * IRAM
- */
-#define IRAM_BASE_ADDR         0x10000000      /* internal ram */
-#define IRAM_SIZE              0x00020000      /* 128 KB */
-
-#define LOW_LEVEL_SRAM_STACK   0x1001E000
-
-/*
- * AIPS 1
- */
-#define AIPS1_BASE_ADDR         0x43F00000
-#define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
-#define MAX_BASE_ADDR           0x43F04000
-#define EVTMON_BASE_ADDR        0x43F08000
-#define CLKCTL_BASE_ADDR        0x43F0C000
-#define I2C1_BASE_ADDR         0x43F80000
-#define I2C3_BASE_ADDR          0x43F84000
-#define ATA_BASE_ADDR           0x43F8C000
-#define UART1_BASE             0x43F90000
-#define UART2_BASE             0x43F94000
-#define I2C2_BASE_ADDR          0x43F98000
-#define CSPI1_BASE_ADDR         0x43FA4000
-#define IOMUXC_BASE_ADDR        0x43FAC000
-
-/*
- * SPBA
- */
-#define SPBA_BASE_ADDR          0x50000000
-#define UART3_BASE             0x5000C000
-#define CSPI2_BASE_ADDR         0x50010000
-#define ATA_DMA_BASE_ADDR       0x50020000
-#define FEC_BASE_ADDR           0x50038000
-#define SPBA_CTRL_BASE_ADDR     0x5003C000
-
-/*
- * AIPS 2
- */
-#define AIPS2_BASE_ADDR         0x53F00000
-#define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
-#define CCM_BASE_ADDR           0x53F80000
-#define GPT1_BASE_ADDR          0x53F90000
-#define EPIT1_BASE_ADDR         0x53F94000
-#define EPIT2_BASE_ADDR         0x53F98000
-#define GPIO3_BASE_ADDR         0x53FA4000
-#define MMC_SDHC1_BASE_ADDR    0x53FB4000
-#define MMC_SDHC2_BASE_ADDR    0x53FB8000
-#define MMC_SDHC3_BASE_ADDR    0x53FBC000
-#define IPU_CTRL_BASE_ADDR     0x53FC0000
-#define GPIO1_BASE_ADDR                0x53FCC000
-#define GPIO2_BASE_ADDR                0x53FD0000
-#define SDMA_BASE_ADDR         0x53FD4000
-#define RTC_BASE_ADDR          0x53FD8000
-#define WDOG1_BASE_ADDR                0x53FDC000
-#define PWM_BASE_ADDR          0x53FE0000
-#define RTIC_BASE_ADDR         0x53FEC000
-#define IIM_BASE_ADDR          0x53FF0000
-#define IMX_USB_BASE           0x53FF4000
-#define IMX_USB_PORT_OFFSET    0x400
-
-#define IMX_CCM_BASE           CCM_BASE_ADDR
-
-/*
- * ROMPATCH and AVIC
- */
-#define ROMPATCH_BASE_ADDR     0x60000000
-#define AVIC_BASE_ADDR         0x68000000
-
-/*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
- */
-#define EXT_MEM_CTRL_BASE      0xB8000000
-#define ESDCTL_BASE_ADDR       0xB8001000
-#define WEIM_BASE_ADDR         0xB8002000
-#define WEIM_CTRL_CS0          WEIM_BASE_ADDR
-#define WEIM_CTRL_CS1          (WEIM_BASE_ADDR + 0x10)
-#define WEIM_CTRL_CS2          (WEIM_BASE_ADDR + 0x20)
-#define WEIM_CTRL_CS3          (WEIM_BASE_ADDR + 0x30)
-#define WEIM_CTRL_CS4          (WEIM_BASE_ADDR + 0x40)
-#define WEIM_CTRL_CS5          (WEIM_BASE_ADDR + 0x50)
-#define M3IF_BASE_ADDR         0xB8003000
-#define EMI_BASE_ADDR          0xB8004000
-
-#define NFC_BASE_ADDR          0xBB000000
-
-/*
- * Memory regions and CS
- */
-#define IPU_MEM_BASE_ADDR      0x70000000
-#define CSD0_BASE_ADDR         0x80000000
-#define CSD1_BASE_ADDR         0x90000000
-#define CS0_BASE_ADDR          0xA0000000
-#define CS1_BASE_ADDR          0xA8000000
-#define CS2_BASE_ADDR          0xB0000000
-#define CS3_BASE_ADDR          0xB2000000
-#define CS4_BASE_ADDR          0xB4000000
-#define CS5_BASE_ADDR          0xB6000000
-
-/*
- * IRQ Controller Register Definitions.
- */
-#define AVIC_NIMASK            0x04
-#define AVIC_INTTYPEH          0x18
-#define AVIC_INTTYPEL          0x1C
-
-/* L210 */
-#define L2CC_BASE_ADDR         0x30000000
-#define L2_CACHE_LINE_SIZE             32
-#define L2_CACHE_CTL_REG               0x100
-#define L2_CACHE_AUX_CTL_REG           0x104
-#define L2_CACHE_SYNC_REG              0x730
-#define L2_CACHE_INV_LINE_REG          0x770
-#define L2_CACHE_INV_WAY_REG           0x77C
-#define L2_CACHE_CLEAN_LINE_REG                0x7B0
-#define L2_CACHE_CLEAN_INV_LINE_REG    0x7F0
-#define L2_CACHE_DBG_CTL_REG           0xF40
-
-#define CLKMODE_AUTO           0
-#define CLKMODE_CONSUMER       1
-
-#define PLL_PD(x)              (((x) & 0xf) << 26)
-#define PLL_MFD(x)             (((x) & 0x3ff) << 16)
-#define PLL_MFI(x)             (((x) & 0xf) << 10)
-#define PLL_MFN(x)             (((x) & 0x3ff) << 0)
-
-#define _PLL_BRM(x)    ((x) << 31)
-#define _PLL_PD(x)     (((x) - 1) << 26)
-#define _PLL_MFD(x)    (((x) - 1) << 16)
-#define _PLL_MFI(x)    ((x) << 10)
-#define _PLL_MFN(x)    (x)
-#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
-       (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
-        _PLL_MFN(mfn))
-
-#define CCM_MPLL_532_HZ        _PLL_SETTING(1, 1, 12, 11, 1)
-#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
-#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
-
-#define CSCR_U(x)      (WEIM_CTRL_CS#x + 0)
-#define CSCR_L(x)      (WEIM_CTRL_CS#x + 4)
-#define CSCR_A(x)      (WEIM_CTRL_CS#x + 8)
-
-#define IIM_SREV       0x24
-#define ROMPATCH_REV   0x40
-
-#define IPU_CONF       IPU_CTRL_BASE_ADDR
-
-#define IPU_CONF_PXL_ENDIAN    (1<<8)
-#define IPU_CONF_DU_EN         (1<<7)
-#define IPU_CONF_DI_EN         (1<<6)
-#define IPU_CONF_ADC_EN                (1<<5)
-#define IPU_CONF_SDC_EN                (1<<4)
-#define IPU_CONF_PF_EN         (1<<3)
-#define IPU_CONF_ROT_EN                (1<<2)
-#define IPU_CONF_IC_EN         (1<<1)
-#define IPU_CONF_CSI_EN                (1<<0)
-
-/*
- * CSPI register definitions
- */
-#define MXC_SPI_BASE_ADDRESSES \
-       0x43fa4000, \
-       0x50010000,
-
-#define GPIO_PORT_NUM          3
-#define GPIO_NUM_PIN           32
-
-#define CHIP_REV_1_0           0x10
-#define CHIP_REV_2_0           0x20
-
-#define BOARD_REV_1_0          0x0
-#define BOARD_REV_2_0          0x1
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-
-/* Clock Control Module (CCM) registers */
-struct ccm_regs {
-       u32 ccmr;       /* Control */
-       u32 pdr0;       /* Post divider 0 */
-       u32 pdr1;       /* Post divider 1 */
-       u32 pdr2;       /* Post divider 2 */
-       u32 pdr3;       /* Post divider 3 */
-       u32 pdr4;       /* Post divider 4 */
-       u32 rcsr;       /* CCM Status */
-       u32 mpctl;      /* Core PLL Control */
-       u32 ppctl;      /* Peripheral PLL Control */
-       u32 acmr;       /* Audio clock mux */
-       u32 cosr;       /* Clock out source */
-       u32 cgr0;       /* Clock Gating Control 0 */
-       u32 cgr1;       /* Clock Gating Control 1 */
-       u32 cgr2;       /* Clock Gating Control 2 */
-       u32 cgr3;       /* Clock Gating Control 3 */
-       u32 reserved;
-       u32 dcvr0;      /* DPTC Comparator 0 */
-       u32 dcvr1;      /* DPTC Comparator 0 */
-       u32 dcvr2;      /* DPTC Comparator 0 */
-       u32 dcvr3;      /* DPTC Comparator 0 */
-       u32 ltr0;       /* Load Tracking 0 */
-       u32 ltr1;       /* Load Tracking 1 */
-       u32 ltr2;       /* Load Tracking 2 */
-       u32 ltr3;       /* Load Tracking 3 */
-       u32 ltbr0;      /* Load Tracking Buffer 0 */
-};
-
-/* IIM control registers */
-struct iim_regs {
-       u32 iim_stat;
-       u32 iim_statm;
-       u32 iim_err;
-       u32 iim_emask;
-       u32 iim_fctl;
-       u32 iim_ua;
-       u32 iim_la;
-       u32 iim_sdat;
-       u32 iim_prev;
-       u32 iim_srev;
-       u32 iim_prg_p;
-       u32 iim_scs0;
-       u32 iim_scs1;
-       u32 iim_scs2;
-       u32 iim_scs3;
-       u32 res1[0x1f1];
-       struct fuse_bank {
-               u32 fuse_regs[0x20];
-               u32 fuse_rsvd[0xe0];
-       } bank[3];
-};
-
-struct fuse_bank0_regs {
-       u32 fuse0_7[8];
-       u32 uid[8];
-       u32 fuse16_31[0x10];
-};
-
-struct fuse_bank1_regs {
-       u32 fuse0_21[0x16];
-       u32 usr;
-       u32 fuse23_31[9];
-};
-
-/* General Purpose Timer (GPT) registers */
-struct gpt_regs {
-       u32 ctrl;       /* control */
-       u32 pre;        /* prescaler */
-       u32 stat;       /* status */
-       u32 intr;       /* interrupt */
-       u32 cmp[3];     /* output compare 1-3 */
-       u32 capt[2];    /* input capture 1-2 */
-       u32 counter;    /* counter */
-};
-
-struct esdc_regs {
-       u32     esdctl0;
-       u32     esdcfg0;
-       u32     esdctl1;
-       u32     esdcfg1;
-       u32     esdmisc;
-       u32     reserved[4];
-       u32     esdcdly[5];
-       u32     esdcdlyl;
-};
-
-#define ESDC_MISC_RST          (1 << 1)
-#define ESDC_MISC_MDDR_EN      (1 << 2)
-#define ESDC_MISC_MDDR_DL_RST  (1 << 3)
-#define ESDC_MISC_DDR_EN       (1 << 8)
-#define ESDC_MISC_DDR2_EN      (1 << 9)
-
-/* Multi-Layer AHB Crossbar Switch (MAX) registers */
-struct max_regs {
-       u32 mpr0;
-       u32 pad00[3];
-       u32 sgpcr0;
-       u32 pad01[59];
-       u32 mpr1;
-       u32 pad02[3];
-       u32 sgpcr1;
-       u32 pad03[59];
-       u32 mpr2;
-       u32 pad04[3];
-       u32 sgpcr2;
-       u32 pad05[59];
-       u32 mpr3;
-       u32 pad06[3];
-       u32 sgpcr3;
-       u32 pad07[59];
-       u32 mpr4;
-       u32 pad08[3];
-       u32 sgpcr4;
-       u32 pad09[251];
-       u32 mgpcr0;
-       u32 pad10[63];
-       u32 mgpcr1;
-       u32 pad11[63];
-       u32 mgpcr2;
-       u32 pad12[63];
-       u32 mgpcr3;
-       u32 pad13[63];
-       u32 mgpcr4;
-       u32 pad14[63];
-       u32 mgpcr5;
-};
-
-/* AHB <-> IP-Bus Interface (AIPS) */
-struct aips_regs {
-       u32 mpr_0_7;
-       u32 mpr_8_15;
-       u32 pad0[6];
-       u32 pacr_0_7;
-       u32 pacr_8_15;
-       u32 pacr_16_23;
-       u32 pacr_24_31;
-       u32 pad1[4];
-       u32 opacr_0_7;
-       u32 opacr_8_15;
-       u32 opacr_16_23;
-       u32 opacr_24_31;
-       u32 opacr_32_39;
-};
-
-/*
- * NFMS bit in RCSR register for pagesize of nandflash
- */
-#define NFMS_BIT               8
-#define NFMS_NF_DWIDTH         14
-#define NFMS_NF_PG_SZ          8
-
-#define CCM_RCSR_NF_16BIT_SEL  (1 << 14)
-
-#endif
-
-/*
- * Generic timer support
- */
-#ifdef CONFIG_MX35_CLK32
-#define        CONFIG_SYS_TIMER_RATE   CONFIG_MX35_CLK32
-#else
-#define        CONFIG_SYS_TIMER_RATE   32768
-#endif
-
-#define CONFIG_SYS_TIMER_COUNTER       (GPT1_BASE_ADDR+36)
-
-#endif /* __ASM_ARCH_MX35_H */

diff --git a/arch/arm/include/asm/arch-mx35/iomux-mx35.h b/arch/arm/include/asm/arch-mx35/iomux-mx35.h
deleted file mode 100644 (file)
index f519c69..0000000
--- a/arch/arm/include/asm/arch-mx35/iomux-mx35.h
+++ /dev/null
@@ -1,1259 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013 ADVANSEE
- * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
- *
- * Based on mainline Linux i.MX iomux-mx35.h file:
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
- */
-
-#ifndef __IOMUX_MX35_H__
-#define __IOMUX_MX35_H__
-
-#include <asm/mach-imx/iomux-v3.h>
-
-/*
- * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
- * See also iomux-v3.h
- */
-
-/*                                                                         PAD    MUX   ALT INPSE PATH PADCTRL */
-enum {
-       MX35_PAD_CAPTURE__GPT_CAPIN1                            = IOMUX_PAD(0x328, 0x004, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CAPTURE__GPT_CMPOUT2                           = IOMUX_PAD(0x328, 0x004, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CAPTURE__CSPI2_SS1                             = IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL),
-       MX35_PAD_CAPTURE__EPIT1_EPITO                           = IOMUX_PAD(0x328, 0x004, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CAPTURE__CCM_CLK32K                            = IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL),
-       MX35_PAD_CAPTURE__GPIO1_4                               = IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL),
-
-       MX35_PAD_COMPARE__GPT_CMPOUT1                           = IOMUX_PAD(0x32c, 0x008, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_COMPARE__GPT_CAPIN2                            = IOMUX_PAD(0x32c, 0x008, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_COMPARE__GPT_CMPOUT3                           = IOMUX_PAD(0x32c, 0x008, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_COMPARE__EPIT2_EPITO                           = IOMUX_PAD(0x32c, 0x008, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_COMPARE__GPIO1_5                               = IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL),
-       MX35_PAD_COMPARE__SDMA_EXTDMA_2                         = IOMUX_PAD(0x32c, 0x008, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_WDOG_RST__WDOG_WDOG_B                          = IOMUX_PAD(0x330, 0x00c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_WDOG_RST__IPU_FLASH_STROBE                     = IOMUX_PAD(0x330, 0x00c, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_WDOG_RST__GPIO1_6                              = IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL),
-
-       MX35_PAD_GPIO1_0__GPIO1_0                               = IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL),
-       MX35_PAD_GPIO1_0__CCM_PMIC_RDY                          = IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL),
-       MX35_PAD_GPIO1_0__OWIRE_LINE                            = IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL),
-       MX35_PAD_GPIO1_0__SDMA_EXTDMA_0                         = IOMUX_PAD(0x334, 0x010, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_GPIO1_1__GPIO1_1                               = IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL),
-       MX35_PAD_GPIO1_1__PWM_PWMO                              = IOMUX_PAD(0x338, 0x014, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_GPIO1_1__CSPI1_SS2                             = IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL),
-       MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT                     = IOMUX_PAD(0x338, 0x014, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_GPIO1_1__SDMA_EXTDMA_1                         = IOMUX_PAD(0x338, 0x014, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_GPIO2_0__GPIO2_0                               = IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL),
-       MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK                    = IOMUX_PAD(0x33c, 0x018, 1, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_GPIO3_0__GPIO3_0                               = IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL),
-       MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK                     = IOMUX_PAD(0x340, 0x01c, 1, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_RESET_IN_B__CCM_RESET_IN_B                     = IOMUX_PAD(0x344, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_POR_B__CCM_POR_B                               = IOMUX_PAD(0x348, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CLKO__CCM_CLKO                                 = IOMUX_PAD(0x34c, 0x020, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CLKO__GPIO1_8                                  = IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL),
-
-       MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0                    = IOMUX_PAD(0x350, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1                    = IOMUX_PAD(0x354, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0                      = IOMUX_PAD(0x358, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1                      = IOMUX_PAD(0x35c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26              = IOMUX_PAD(0x360, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_VSTBY__CCM_VSTBY                               = IOMUX_PAD(0x364, 0x024, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_VSTBY__GPIO1_7                                 = IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL),
-
-       MX35_PAD_A0__EMI_EIM_DA_L_0                             = IOMUX_PAD(0x368, 0x028, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A1__EMI_EIM_DA_L_1                             = IOMUX_PAD(0x36c, 0x02c, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A2__EMI_EIM_DA_L_2                             = IOMUX_PAD(0x370, 0x030, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A3__EMI_EIM_DA_L_3                             = IOMUX_PAD(0x374, 0x034, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A4__EMI_EIM_DA_L_4                             = IOMUX_PAD(0x378, 0x038, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A5__EMI_EIM_DA_L_5                             = IOMUX_PAD(0x37c, 0x03c, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A6__EMI_EIM_DA_L_6                             = IOMUX_PAD(0x380, 0x040, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A7__EMI_EIM_DA_L_7                             = IOMUX_PAD(0x384, 0x044, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A8__EMI_EIM_DA_H_8                             = IOMUX_PAD(0x388, 0x048, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A9__EMI_EIM_DA_H_9                             = IOMUX_PAD(0x38c, 0x04c, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A10__EMI_EIM_DA_H_10                           = IOMUX_PAD(0x390, 0x050, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_MA10__EMI_MA10                                 = IOMUX_PAD(0x394, 0x054, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A11__EMI_EIM_DA_H_11                           = IOMUX_PAD(0x398, 0x058, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A12__EMI_EIM_DA_H_12                           = IOMUX_PAD(0x39c, 0x05c, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A13__EMI_EIM_DA_H_13                           = IOMUX_PAD(0x3a0, 0x060, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A14__EMI_EIM_DA_H2_14                          = IOMUX_PAD(0x3a4, 0x064, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A15__EMI_EIM_DA_H2_15                          = IOMUX_PAD(0x3a8, 0x068, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A16__EMI_EIM_A_16                              = IOMUX_PAD(0x3ac, 0x06c, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A17__EMI_EIM_A_17                              = IOMUX_PAD(0x3b0, 0x070, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A18__EMI_EIM_A_18                              = IOMUX_PAD(0x3b4, 0x074, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A19__EMI_EIM_A_19                              = IOMUX_PAD(0x3b8, 0x078, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A20__EMI_EIM_A_20                              = IOMUX_PAD(0x3bc, 0x07c, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A21__EMI_EIM_A_21                              = IOMUX_PAD(0x3c0, 0x080, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A22__EMI_EIM_A_22                              = IOMUX_PAD(0x3c4, 0x084, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A23__EMI_EIM_A_23                              = IOMUX_PAD(0x3c8, 0x088, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A24__EMI_EIM_A_24                              = IOMUX_PAD(0x3cc, 0x08c, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_A25__EMI_EIM_A_25                              = IOMUX_PAD(0x3d0, 0x090, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SDBA1__EMI_EIM_SDBA1                           = IOMUX_PAD(0x3d4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SDBA0__EMI_EIM_SDBA0                           = IOMUX_PAD(0x3d8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD0__EMI_DRAM_D_0                              = IOMUX_PAD(0x3dc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD1__EMI_DRAM_D_1                              = IOMUX_PAD(0x3e0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD2__EMI_DRAM_D_2                              = IOMUX_PAD(0x3e4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD3__EMI_DRAM_D_3                              = IOMUX_PAD(0x3e8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD4__EMI_DRAM_D_4                              = IOMUX_PAD(0x3ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD5__EMI_DRAM_D_5                              = IOMUX_PAD(0x3f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD6__EMI_DRAM_D_6                              = IOMUX_PAD(0x3f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD7__EMI_DRAM_D_7                              = IOMUX_PAD(0x3f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD8__EMI_DRAM_D_8                              = IOMUX_PAD(0x3fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD9__EMI_DRAM_D_9                              = IOMUX_PAD(0x400, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD10__EMI_DRAM_D_10                            = IOMUX_PAD(0x404, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD11__EMI_DRAM_D_11                            = IOMUX_PAD(0x408, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD12__EMI_DRAM_D_12                            = IOMUX_PAD(0x40c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD13__EMI_DRAM_D_13                            = IOMUX_PAD(0x410, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD14__EMI_DRAM_D_14                            = IOMUX_PAD(0x414, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD15__EMI_DRAM_D_15                            = IOMUX_PAD(0x418, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD16__EMI_DRAM_D_16                            = IOMUX_PAD(0x41c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD17__EMI_DRAM_D_17                            = IOMUX_PAD(0x420, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD18__EMI_DRAM_D_18                            = IOMUX_PAD(0x424, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD19__EMI_DRAM_D_19                            = IOMUX_PAD(0x428, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD20__EMI_DRAM_D_20                            = IOMUX_PAD(0x42c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD21__EMI_DRAM_D_21                            = IOMUX_PAD(0x430, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD22__EMI_DRAM_D_22                            = IOMUX_PAD(0x434, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD23__EMI_DRAM_D_23                            = IOMUX_PAD(0x438, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD24__EMI_DRAM_D_24                            = IOMUX_PAD(0x43c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD25__EMI_DRAM_D_25                            = IOMUX_PAD(0x440, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD26__EMI_DRAM_D_26                            = IOMUX_PAD(0x444, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD27__EMI_DRAM_D_27                            = IOMUX_PAD(0x448, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD28__EMI_DRAM_D_28                            = IOMUX_PAD(0x44c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD29__EMI_DRAM_D_29                            = IOMUX_PAD(0x450, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD30__EMI_DRAM_D_30                            = IOMUX_PAD(0x454, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD31__EMI_DRAM_D_31                            = IOMUX_PAD(0x458, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_DQM0__EMI_DRAM_DQM_0                           = IOMUX_PAD(0x45c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_DQM1__EMI_DRAM_DQM_1                           = IOMUX_PAD(0x460, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_DQM2__EMI_DRAM_DQM_2                           = IOMUX_PAD(0x464, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_DQM3__EMI_DRAM_DQM_3                           = IOMUX_PAD(0x468, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_EB0__EMI_EIM_EB0_B                             = IOMUX_PAD(0x46c, 0x094, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_EB1__EMI_EIM_EB1_B                             = IOMUX_PAD(0x470, 0x098, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_OE__EMI_EIM_OE                                 = IOMUX_PAD(0x474, 0x09c, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CS0__EMI_EIM_CS0                               = IOMUX_PAD(0x478, 0x0a0, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CS1__EMI_EIM_CS1                               = IOMUX_PAD(0x47c, 0x0a4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CS1__EMI_NANDF_CE3                             = IOMUX_PAD(0x47c, 0x0a4, 3, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CS2__EMI_EIM_CS2                               = IOMUX_PAD(0x480, 0x0a8, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CS3__EMI_EIM_CS3                               = IOMUX_PAD(0x484, 0x0ac, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CS4__EMI_EIM_CS4                               = IOMUX_PAD(0x488, 0x0b0, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CS4__EMI_DTACK_B                               = IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL),
-       MX35_PAD_CS4__EMI_NANDF_CE1                             = IOMUX_PAD(0x488, 0x0b0, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CS4__GPIO1_20                                  = IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL),
-
-       MX35_PAD_CS5__EMI_EIM_CS5                               = IOMUX_PAD(0x48c, 0x0b4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CS5__CSPI2_SS2                                 = IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL),
-       MX35_PAD_CS5__CSPI1_SS2                                 = IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL),
-       MX35_PAD_CS5__EMI_NANDF_CE2                             = IOMUX_PAD(0x48c, 0x0b4, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CS5__GPIO1_21                                  = IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL),
-
-       MX35_PAD_NF_CE0__EMI_NANDF_CE0                          = IOMUX_PAD(0x490, 0x0b8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_NF_CE0__GPIO1_22                               = IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL),
-
-       MX35_PAD_ECB__EMI_EIM_ECB                               = IOMUX_PAD(0x494, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LBA__EMI_EIM_LBA                               = IOMUX_PAD(0x498, 0x0bc, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_BCLK__EMI_EIM_BCLK                             = IOMUX_PAD(0x49c, 0x0c0, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_RW__EMI_EIM_RW                                 = IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_RAS__EMI_DRAM_RAS                              = IOMUX_PAD(0x4a4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CAS__EMI_DRAM_CAS                              = IOMUX_PAD(0x4a8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SDWE__EMI_DRAM_SDWE                            = IOMUX_PAD(0x4ac, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0                       = IOMUX_PAD(0x4b0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1                       = IOMUX_PAD(0x4b4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SDCLK__EMI_DRAM_SDCLK                          = IOMUX_PAD(0x4b8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SDQS0__EMI_DRAM_SDQS_0                         = IOMUX_PAD(0x4bc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SDQS1__EMI_DRAM_SDQS_1                         = IOMUX_PAD(0x4c0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SDQS2__EMI_DRAM_SDQS_2                         = IOMUX_PAD(0x4c4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SDQS3__EMI_DRAM_SDQS_3                         = IOMUX_PAD(0x4c8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_NFWE_B__EMI_NANDF_WE_B                         = IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3                   = IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL),
-       MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC                     = IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL),
-       MX35_PAD_NFWE_B__GPIO2_18                               = IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL),
-       MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0                     = IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_NFRE_B__EMI_NANDF_RE_B                         = IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR                      = IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL),
-       MX35_PAD_NFRE_B__IPU_DISPB_BCLK                         = IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_NFRE_B__GPIO2_19                               = IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL),
-       MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1                     = IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_NFALE__EMI_NANDF_ALE                           = IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_NFALE__USB_TOP_USBH2_STP                       = IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_NFALE__IPU_DISPB_CS0                           = IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_NFALE__GPIO2_20                                = IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL),
-       MX35_PAD_NFALE__ARM11P_TOP_TRACE_2                      = IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_NFCLE__EMI_NANDF_CLE                           = IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_NFCLE__USB_TOP_USBH2_NXT                       = IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL),
-       MX35_PAD_NFCLE__IPU_DISPB_PAR_RS                        = IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_NFCLE__GPIO2_21                                = IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL),
-       MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3                      = IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_NFWP_B__EMI_NANDF_WP_B                         = IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7                   = IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL),
-       MX35_PAD_NFWP_B__IPU_DISPB_WR                           = IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_NFWP_B__GPIO2_22                               = IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL),
-       MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL                       = IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_NFRB__EMI_NANDF_RB                             = IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_NFRB__IPU_DISPB_RD                             = IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_NFRB__GPIO2_23                                 = IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL),
-       MX35_PAD_NFRB__ARM11P_TOP_TRCLK                         = IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D15__EMI_EIM_D_15                              = IOMUX_PAD(0x4e4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D14__EMI_EIM_D_14                              = IOMUX_PAD(0x4e8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D13__EMI_EIM_D_13                              = IOMUX_PAD(0x4ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D12__EMI_EIM_D_12                              = IOMUX_PAD(0x4f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D11__EMI_EIM_D_11                              = IOMUX_PAD(0x4f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D10__EMI_EIM_D_10                              = IOMUX_PAD(0x4f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D9__EMI_EIM_D_9                                = IOMUX_PAD(0x4fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D8__EMI_EIM_D_8                                = IOMUX_PAD(0x500, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D7__EMI_EIM_D_7                                = IOMUX_PAD(0x504, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D6__EMI_EIM_D_6                                = IOMUX_PAD(0x508, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D5__EMI_EIM_D_5                                = IOMUX_PAD(0x50c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D4__EMI_EIM_D_4                                = IOMUX_PAD(0x510, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D3__EMI_EIM_D_3                                = IOMUX_PAD(0x514, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D2__EMI_EIM_D_2                                = IOMUX_PAD(0x518, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D1__EMI_EIM_D_1                                = IOMUX_PAD(0x51c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D0__EMI_EIM_D_0                                = IOMUX_PAD(0x520, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSI_D8__IPU_CSI_D_8                            = IOMUX_PAD(0x524, 0x0e0, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSI_D8__KPP_COL_0                              = IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL),
-       MX35_PAD_CSI_D8__GPIO1_20                               = IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL),
-       MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13                  = IOMUX_PAD(0x524, 0x0e0, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSI_D9__IPU_CSI_D_9                            = IOMUX_PAD(0x528, 0x0e4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSI_D9__KPP_COL_1                              = IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL),
-       MX35_PAD_CSI_D9__GPIO1_21                               = IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL),
-       MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14                  = IOMUX_PAD(0x528, 0x0e4, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSI_D10__IPU_CSI_D_10                          = IOMUX_PAD(0x52c, 0x0e8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSI_D10__KPP_COL_2                             = IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL),
-       MX35_PAD_CSI_D10__GPIO1_22                              = IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL),
-       MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15                 = IOMUX_PAD(0x52c, 0x0e8, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSI_D11__IPU_CSI_D_11                          = IOMUX_PAD(0x530, 0x0ec, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSI_D11__KPP_COL_3                             = IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL),
-       MX35_PAD_CSI_D11__GPIO1_23                              = IOMUX_PAD(0x530, 0x0ec, 5, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSI_D12__IPU_CSI_D_12                          = IOMUX_PAD(0x534, 0x0f0, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSI_D12__KPP_ROW_0                             = IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL),
-       MX35_PAD_CSI_D12__GPIO1_24                              = IOMUX_PAD(0x534, 0x0f0, 5, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSI_D13__IPU_CSI_D_13                          = IOMUX_PAD(0x538, 0x0f4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSI_D13__KPP_ROW_1                             = IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL),
-       MX35_PAD_CSI_D13__GPIO1_25                              = IOMUX_PAD(0x538, 0x0f4, 5, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSI_D14__IPU_CSI_D_14                          = IOMUX_PAD(0x53c, 0x0f8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSI_D14__KPP_ROW_2                             = IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL),
-       MX35_PAD_CSI_D14__GPIO1_26                              = IOMUX_PAD(0x53c, 0x0f8, 5, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSI_D15__IPU_CSI_D_15                          = IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL),
-       MX35_PAD_CSI_D15__KPP_ROW_3                             = IOMUX_PAD(0x540, 0x0fc, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSI_D15__GPIO1_27                              = IOMUX_PAD(0x540, 0x0fc, 5, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSI_MCLK__IPU_CSI_MCLK                         = IOMUX_PAD(0x544, 0x100, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSI_MCLK__GPIO1_28                             = IOMUX_PAD(0x544, 0x100, 5, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC                       = IOMUX_PAD(0x548, 0x104, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSI_VSYNC__GPIO1_29                            = IOMUX_PAD(0x548, 0x104, 5, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC                       = IOMUX_PAD(0x54c, 0x108, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSI_HSYNC__GPIO1_30                            = IOMUX_PAD(0x54c, 0x108, 5, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK                     = IOMUX_PAD(0x550, 0x10c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSI_PIXCLK__GPIO1_31                           = IOMUX_PAD(0x550, 0x10c, 5, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_I2C1_CLK__I2C1_SCL                             = IOMUX_PAD(0x554, 0x110, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_I2C1_CLK__GPIO2_24                             = IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL),
-       MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK                      = IOMUX_PAD(0x554, 0x110, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_I2C1_DAT__I2C1_SDA                             = IOMUX_PAD(0x558, 0x114, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_I2C1_DAT__GPIO2_25                             = IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL),
-
-       MX35_PAD_I2C2_CLK__I2C2_SCL                             = IOMUX_PAD(0x55c, 0x118, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_I2C2_CLK__CAN1_TXCAN                           = IOMUX_PAD(0x55c, 0x118, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR                    = IOMUX_PAD(0x55c, 0x118, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_I2C2_CLK__GPIO2_26                             = IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL),
-       MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2              = IOMUX_PAD(0x55c, 0x118, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_I2C2_DAT__I2C2_SDA                             = IOMUX_PAD(0x560, 0x11c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_I2C2_DAT__CAN1_RXCAN                           = IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL),
-       MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC                     = IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL),
-       MX35_PAD_I2C2_DAT__GPIO2_27                             = IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL),
-       MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3              = IOMUX_PAD(0x560, 0x11c, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_STXD4__AUDMUX_AUD4_TXD                         = IOMUX_PAD(0x564, 0x120, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_STXD4__GPIO2_28                                = IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL),
-       MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0                = IOMUX_PAD(0x564, 0x120, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SRXD4__AUDMUX_AUD4_RXD                         = IOMUX_PAD(0x568, 0x124, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SRXD4__GPIO2_29                                = IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL),
-       MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1                = IOMUX_PAD(0x568, 0x124, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SCK4__AUDMUX_AUD4_TXC                          = IOMUX_PAD(0x56c, 0x128, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SCK4__GPIO2_30                                 = IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL),
-       MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2                 = IOMUX_PAD(0x56c, 0x128, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS                       = IOMUX_PAD(0x570, 0x12c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_STXFS4__GPIO2_31                               = IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL),
-       MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3               = IOMUX_PAD(0x570, 0x12c, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_STXD5__AUDMUX_AUD5_TXD                         = IOMUX_PAD(0x574, 0x130, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_STXD5__SPDIF_SPDIF_OUT1                        = IOMUX_PAD(0x574, 0x130, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_STXD5__CSPI2_MOSI                              = IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL),
-       MX35_PAD_STXD5__GPIO1_0                                 = IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL),
-       MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4                = IOMUX_PAD(0x574, 0x130, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SRXD5__AUDMUX_AUD5_RXD                         = IOMUX_PAD(0x578, 0x134, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SRXD5__SPDIF_SPDIF_IN1                         = IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL),
-       MX35_PAD_SRXD5__CSPI2_MISO                              = IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL),
-       MX35_PAD_SRXD5__GPIO1_1                                 = IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL),
-       MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5                = IOMUX_PAD(0x578, 0x134, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SCK5__AUDMUX_AUD5_TXC                          = IOMUX_PAD(0x57c, 0x138, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK                       = IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL),
-       MX35_PAD_SCK5__CSPI2_SCLK                               = IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL),
-       MX35_PAD_SCK5__GPIO1_2                                  = IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL),
-       MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6                 = IOMUX_PAD(0x57c, 0x138, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS                       = IOMUX_PAD(0x580, 0x13c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_STXFS5__CSPI2_RDY                              = IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL),
-       MX35_PAD_STXFS5__GPIO1_3                                = IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL),
-       MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7               = IOMUX_PAD(0x580, 0x13c, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SCKR__ESAI_SCKR                                = IOMUX_PAD(0x584, 0x140, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SCKR__GPIO1_4                                  = IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL),
-       MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10                    = IOMUX_PAD(0x584, 0x140, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FSR__ESAI_FSR                                  = IOMUX_PAD(0x588, 0x144, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FSR__GPIO1_5                                   = IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL),
-       MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11                     = IOMUX_PAD(0x588, 0x144, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_HCKR__ESAI_HCKR                                = IOMUX_PAD(0x58c, 0x148, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_HCKR__AUDMUX_AUD5_RXFS                         = IOMUX_PAD(0x58c, 0x148, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_HCKR__CSPI2_SS0                                = IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL),
-       MX35_PAD_HCKR__IPU_FLASH_STROBE                         = IOMUX_PAD(0x58c, 0x148, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_HCKR__GPIO1_6                                  = IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL),
-       MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12                    = IOMUX_PAD(0x58c, 0x148, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SCKT__ESAI_SCKT                                = IOMUX_PAD(0x590, 0x14c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SCKT__GPIO1_7                                  = IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL),
-       MX35_PAD_SCKT__IPU_CSI_D_0                              = IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL),
-       MX35_PAD_SCKT__KPP_ROW_2                                = IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL),
-
-       MX35_PAD_FST__ESAI_FST                                  = IOMUX_PAD(0x594, 0x150, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FST__GPIO1_8                                   = IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL),
-       MX35_PAD_FST__IPU_CSI_D_1                               = IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL),
-       MX35_PAD_FST__KPP_ROW_3                                 = IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL),
-
-       MX35_PAD_HCKT__ESAI_HCKT                                = IOMUX_PAD(0x598, 0x154, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_HCKT__AUDMUX_AUD5_RXC                          = IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL),
-       MX35_PAD_HCKT__GPIO1_9                                  = IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL),
-       MX35_PAD_HCKT__IPU_CSI_D_2                              = IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL),
-       MX35_PAD_HCKT__KPP_COL_3                                = IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL),
-
-       MX35_PAD_TX5_RX0__ESAI_TX5_RX0                          = IOMUX_PAD(0x59c, 0x158, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC                       = IOMUX_PAD(0x59c, 0x158, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX5_RX0__CSPI2_SS2                             = IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL),
-       MX35_PAD_TX5_RX0__CAN2_TXCAN                            = IOMUX_PAD(0x59c, 0x158, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX5_RX0__UART2_DTR                             = IOMUX_PAD(0x59c, 0x158, 4, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX5_RX0__GPIO1_10                              = IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL),
-       MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0              = IOMUX_PAD(0x59c, 0x158, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_TX4_RX1__ESAI_TX4_RX1                          = IOMUX_PAD(0x5a0, 0x15c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS                      = IOMUX_PAD(0x5a0, 0x15c, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX4_RX1__CSPI2_SS3                             = IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL),
-       MX35_PAD_TX4_RX1__CAN2_RXCAN                            = IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL),
-       MX35_PAD_TX4_RX1__UART2_DSR                             = IOMUX_PAD(0x5a0, 0x15c, 4, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX4_RX1__GPIO1_11                              = IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL),
-       MX35_PAD_TX4_RX1__IPU_CSI_D_3                           = IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL),
-       MX35_PAD_TX4_RX1__KPP_ROW_0                             = IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL),
-
-       MX35_PAD_TX3_RX2__ESAI_TX3_RX2                          = IOMUX_PAD(0x5a4, 0x160, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX3_RX2__I2C3_SCL                              = IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL),
-       MX35_PAD_TX3_RX2__EMI_NANDF_CE1                         = IOMUX_PAD(0x5a4, 0x160, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX3_RX2__GPIO1_12                              = IOMUX_PAD(0x5a4, 0x160, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX3_RX2__IPU_CSI_D_4                           = IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL),
-       MX35_PAD_TX3_RX2__KPP_ROW_1                             = IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL),
-
-       MX35_PAD_TX2_RX3__ESAI_TX2_RX3                          = IOMUX_PAD(0x5a8, 0x164, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX2_RX3__I2C3_SDA                              = IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL),
-       MX35_PAD_TX2_RX3__EMI_NANDF_CE2                         = IOMUX_PAD(0x5a8, 0x164, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX2_RX3__GPIO1_13                              = IOMUX_PAD(0x5a8, 0x164, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX2_RX3__IPU_CSI_D_5                           = IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL),
-       MX35_PAD_TX2_RX3__KPP_COL_0                             = IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL),
-
-       MX35_PAD_TX1__ESAI_TX1                                  = IOMUX_PAD(0x5ac, 0x168, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX1__CCM_PMIC_RDY                              = IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL),
-       MX35_PAD_TX1__CSPI1_SS2                                 = IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL),
-       MX35_PAD_TX1__EMI_NANDF_CE3                             = IOMUX_PAD(0x5ac, 0x168, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX1__UART2_RI                                  = IOMUX_PAD(0x5ac, 0x168, 4, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX1__GPIO1_14                                  = IOMUX_PAD(0x5ac, 0x168, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX1__IPU_CSI_D_6                               = IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL),
-       MX35_PAD_TX1__KPP_COL_1                                 = IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL),
-
-       MX35_PAD_TX0__ESAI_TX0                                  = IOMUX_PAD(0x5b0, 0x16c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK                        = IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL),
-       MX35_PAD_TX0__CSPI1_SS3                                 = IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL),
-       MX35_PAD_TX0__EMI_DTACK_B                               = IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL),
-       MX35_PAD_TX0__UART2_DCD                                 = IOMUX_PAD(0x5b0, 0x16c, 4, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX0__GPIO1_15                                  = IOMUX_PAD(0x5b0, 0x16c, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TX0__IPU_CSI_D_7                               = IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL),
-       MX35_PAD_TX0__KPP_COL_2                                 = IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL),
-
-       MX35_PAD_CSPI1_MOSI__CSPI1_MOSI                         = IOMUX_PAD(0x5b4, 0x170, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_MOSI__GPIO1_16                           = IOMUX_PAD(0x5b4, 0x170, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2                = IOMUX_PAD(0x5b4, 0x170, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSPI1_MISO__CSPI1_MISO                         = IOMUX_PAD(0x5b8, 0x174, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_MISO__GPIO1_17                           = IOMUX_PAD(0x5b8, 0x174, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3                = IOMUX_PAD(0x5b8, 0x174, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSPI1_SS0__CSPI1_SS0                           = IOMUX_PAD(0x5bc, 0x178, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_SS0__OWIRE_LINE                          = IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_SS0__CSPI2_SS3                           = IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_SS0__GPIO1_18                            = IOMUX_PAD(0x5bc, 0x178, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4                 = IOMUX_PAD(0x5bc, 0x178, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSPI1_SS1__CSPI1_SS1                           = IOMUX_PAD(0x5c0, 0x17c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_SS1__PWM_PWMO                            = IOMUX_PAD(0x5c0, 0x17c, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_SS1__CCM_CLK32K                          = IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_SS1__GPIO1_19                            = IOMUX_PAD(0x5c0, 0x17c, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_SS1__IPU_DIAGB_29                        = IOMUX_PAD(0x5c0, 0x17c, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5                 = IOMUX_PAD(0x5c0, 0x17c, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSPI1_SCLK__CSPI1_SCLK                         = IOMUX_PAD(0x5c4, 0x180, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_SCLK__GPIO3_4                            = IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30                       = IOMUX_PAD(0x5c4, 0x180, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1           = IOMUX_PAD(0x5c4, 0x180, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY                       = IOMUX_PAD(0x5c8, 0x184, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_SPI_RDY__GPIO3_5                         = IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31                    = IOMUX_PAD(0x5c8, 0x184, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2        = IOMUX_PAD(0x5c8, 0x184, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_RXD1__UART1_RXD_MUX                            = IOMUX_PAD(0x5cc, 0x188, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_RXD1__CSPI2_MOSI                               = IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL),
-       MX35_PAD_RXD1__KPP_COL_4                                = IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL),
-       MX35_PAD_RXD1__GPIO3_6                                  = IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL),
-       MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16                    = IOMUX_PAD(0x5cc, 0x188, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_TXD1__UART1_TXD_MUX                            = IOMUX_PAD(0x5d0, 0x18c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TXD1__CSPI2_MISO                               = IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL),
-       MX35_PAD_TXD1__KPP_COL_5                                = IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL),
-       MX35_PAD_TXD1__GPIO3_7                                  = IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL),
-       MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17                    = IOMUX_PAD(0x5d0, 0x18c, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_RTS1__UART1_RTS                                = IOMUX_PAD(0x5d4, 0x190, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_RTS1__CSPI2_SCLK                               = IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL),
-       MX35_PAD_RTS1__I2C3_SCL                                 = IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL),
-       MX35_PAD_RTS1__IPU_CSI_D_0                              = IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL),
-       MX35_PAD_RTS1__KPP_COL_6                                = IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL),
-       MX35_PAD_RTS1__GPIO3_8                                  = IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL),
-       MX35_PAD_RTS1__EMI_NANDF_CE1                            = IOMUX_PAD(0x5d4, 0x190, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18                    = IOMUX_PAD(0x5d4, 0x190, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CTS1__UART1_CTS                                = IOMUX_PAD(0x5d8, 0x194, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CTS1__CSPI2_RDY                                = IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL),
-       MX35_PAD_CTS1__I2C3_SDA                                 = IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL),
-       MX35_PAD_CTS1__IPU_CSI_D_1                              = IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL),
-       MX35_PAD_CTS1__KPP_COL_7                                = IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL),
-       MX35_PAD_CTS1__GPIO3_9                                  = IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL),
-       MX35_PAD_CTS1__EMI_NANDF_CE2                            = IOMUX_PAD(0x5d8, 0x194, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19                    = IOMUX_PAD(0x5d8, 0x194, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_RXD2__UART2_RXD_MUX                            = IOMUX_PAD(0x5dc, 0x198, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_RXD2__KPP_ROW_4                                = IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL),
-       MX35_PAD_RXD2__GPIO3_10                                 = IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL),
-
-       MX35_PAD_TXD2__UART2_TXD_MUX                            = IOMUX_PAD(0x5e0, 0x19c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK                       = IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL),
-       MX35_PAD_TXD2__KPP_ROW_5                                = IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL),
-       MX35_PAD_TXD2__GPIO3_11                                 = IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL),
-
-       MX35_PAD_RTS2__UART2_RTS                                = IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_RTS2__SPDIF_SPDIF_IN1                          = IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL),
-       MX35_PAD_RTS2__CAN2_RXCAN                               = IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL),
-       MX35_PAD_RTS2__IPU_CSI_D_2                              = IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL),
-       MX35_PAD_RTS2__KPP_ROW_6                                = IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL),
-       MX35_PAD_RTS2__GPIO3_12                                 = IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL),
-       MX35_PAD_RTS2__AUDMUX_AUD5_RXC                          = IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_RTS2__UART3_RXD_MUX                            = IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL),
-
-       MX35_PAD_CTS2__UART2_CTS                                = IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CTS2__SPDIF_SPDIF_OUT1                         = IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CTS2__CAN2_TXCAN                               = IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CTS2__IPU_CSI_D_3                              = IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL),
-       MX35_PAD_CTS2__KPP_ROW_7                                = IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL),
-       MX35_PAD_CTS2__GPIO3_13                                 = IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL),
-       MX35_PAD_CTS2__AUDMUX_AUD5_RXFS                         = IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CTS2__UART3_TXD_MUX                            = IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_RTCK__ARM11P_TOP_RTCK                          = IOMUX_PAD(0x5ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_TCK__SJC_TCK                                   = IOMUX_PAD(0x5f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_TMS__SJC_TMS                                   = IOMUX_PAD(0x5f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_TDI__SJC_TDI                                   = IOMUX_PAD(0x5f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_TDO__SJC_TDO                                   = IOMUX_PAD(0x5fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_TRSTB__SJC_TRSTB                               = IOMUX_PAD(0x600, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_DE_B__SJC_DE_B                                 = IOMUX_PAD(0x604, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SJC_MOD__SJC_MOD                               = IOMUX_PAD(0x608, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR                 = IOMUX_PAD(0x60c, 0x1a8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR                  = IOMUX_PAD(0x60c, 0x1a8, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_USBOTG_PWR__GPIO3_14                           = IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL),
-
-       MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC                   = IOMUX_PAD(0x610, 0x1ac, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC                    = IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL),
-       MX35_PAD_USBOTG_OC__GPIO3_15                            = IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL),
-
-       MX35_PAD_LD0__IPU_DISPB_DAT_0                           = IOMUX_PAD(0x614, 0x1b0, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD0__GPIO2_0                                   = IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL),
-       MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0                      = IOMUX_PAD(0x614, 0x1b0, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD1__IPU_DISPB_DAT_1                           = IOMUX_PAD(0x618, 0x1b4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD1__GPIO2_1                                   = IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL),
-       MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1                      = IOMUX_PAD(0x618, 0x1b4, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD2__IPU_DISPB_DAT_2                           = IOMUX_PAD(0x61c, 0x1b8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD2__GPIO2_2                                   = IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL),
-       MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2                      = IOMUX_PAD(0x61c, 0x1b8, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD3__IPU_DISPB_DAT_3                           = IOMUX_PAD(0x620, 0x1bc, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD3__GPIO2_3                                   = IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL),
-       MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3                      = IOMUX_PAD(0x620, 0x1bc, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD4__IPU_DISPB_DAT_4                           = IOMUX_PAD(0x624, 0x1c0, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD4__GPIO2_4                                   = IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL),
-       MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4                      = IOMUX_PAD(0x624, 0x1c0, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD5__IPU_DISPB_DAT_5                           = IOMUX_PAD(0x628, 0x1c4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD5__GPIO2_5                                   = IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL),
-       MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5                      = IOMUX_PAD(0x628, 0x1c4, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD6__IPU_DISPB_DAT_6                           = IOMUX_PAD(0x62c, 0x1c8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD6__GPIO2_6                                   = IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL),
-       MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6                      = IOMUX_PAD(0x62c, 0x1c8, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD7__IPU_DISPB_DAT_7                           = IOMUX_PAD(0x630, 0x1cc, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD7__GPIO2_7                                   = IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL),
-       MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7                      = IOMUX_PAD(0x630, 0x1cc, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD8__IPU_DISPB_DAT_8                           = IOMUX_PAD(0x634, 0x1d0, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD8__GPIO2_8                                   = IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL),
-       MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8                      = IOMUX_PAD(0x634, 0x1d0, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD9__IPU_DISPB_DAT_9                           = IOMUX_PAD(0x638, 0x1d4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD9__GPIO2_9                                   = IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL),
-       MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9                      = IOMUX_PAD(0x638, 0x1d4, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD10__IPU_DISPB_DAT_10                         = IOMUX_PAD(0x63c, 0x1d8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD10__GPIO2_10                                 = IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL),
-       MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10                    = IOMUX_PAD(0x63c, 0x1d8, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD11__IPU_DISPB_DAT_11                         = IOMUX_PAD(0x640, 0x1dc, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD11__GPIO2_11                                 = IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL),
-       MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11                    = IOMUX_PAD(0x640, 0x1dc, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD11__ARM11P_TOP_TRACE_4                       = IOMUX_PAD(0x640, 0x1dc, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD12__IPU_DISPB_DAT_12                         = IOMUX_PAD(0x644, 0x1e0, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD12__GPIO2_12                                 = IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL),
-       MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12                    = IOMUX_PAD(0x644, 0x1e0, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD12__ARM11P_TOP_TRACE_5                       = IOMUX_PAD(0x644, 0x1e0, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD13__IPU_DISPB_DAT_13                         = IOMUX_PAD(0x648, 0x1e4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD13__GPIO2_13                                 = IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL),
-       MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13                    = IOMUX_PAD(0x648, 0x1e4, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD13__ARM11P_TOP_TRACE_6                       = IOMUX_PAD(0x648, 0x1e4, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD14__IPU_DISPB_DAT_14                         = IOMUX_PAD(0x64c, 0x1e8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD14__GPIO2_14                                 = IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL),
-       MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0          = IOMUX_PAD(0x64c, 0x1e8, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD14__ARM11P_TOP_TRACE_7                       = IOMUX_PAD(0x64c, 0x1e8, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD15__IPU_DISPB_DAT_15                         = IOMUX_PAD(0x650, 0x1ec, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD15__GPIO2_15                                 = IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL),
-       MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1          = IOMUX_PAD(0x650, 0x1ec, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD15__ARM11P_TOP_TRACE_8                       = IOMUX_PAD(0x650, 0x1ec, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD16__IPU_DISPB_DAT_16                         = IOMUX_PAD(0x654, 0x1f0, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD16__IPU_DISPB_D12_VSYNC                      = IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL),
-       MX35_PAD_LD16__GPIO2_16                                 = IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL),
-       MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2          = IOMUX_PAD(0x654, 0x1f0, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD16__ARM11P_TOP_TRACE_9                       = IOMUX_PAD(0x654, 0x1f0, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD17__IPU_DISPB_DAT_17                         = IOMUX_PAD(0x658, 0x1f4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD17__IPU_DISPB_CS2                            = IOMUX_PAD(0x658, 0x1f4, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD17__GPIO2_17                                 = IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL),
-       MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3          = IOMUX_PAD(0x658, 0x1f4, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD17__ARM11P_TOP_TRACE_10                      = IOMUX_PAD(0x658, 0x1f4, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD18__IPU_DISPB_DAT_18                         = IOMUX_PAD(0x65c, 0x1f8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD18__IPU_DISPB_D0_VSYNC                       = IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL),
-       MX35_PAD_LD18__IPU_DISPB_D12_VSYNC                      = IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL),
-       MX35_PAD_LD18__ESDHC3_CMD                               = IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL),
-       MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3                    = IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL),
-       MX35_PAD_LD18__GPIO3_24                                 = IOMUX_PAD(0x65c, 0x1f8, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4          = IOMUX_PAD(0x65c, 0x1f8, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD18__ARM11P_TOP_TRACE_11                      = IOMUX_PAD(0x65c, 0x1f8, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD19__IPU_DISPB_DAT_19                         = IOMUX_PAD(0x660, 0x1fc, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD19__IPU_DISPB_BCLK                           = IOMUX_PAD(0x660, 0x1fc, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD19__IPU_DISPB_CS1                            = IOMUX_PAD(0x660, 0x1fc, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD19__ESDHC3_CLK                               = IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL),
-       MX35_PAD_LD19__USB_TOP_USBOTG_DIR                       = IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL),
-       MX35_PAD_LD19__GPIO3_25                                 = IOMUX_PAD(0x660, 0x1fc, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5          = IOMUX_PAD(0x660, 0x1fc, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD19__ARM11P_TOP_TRACE_12                      = IOMUX_PAD(0x660, 0x1fc, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD20__IPU_DISPB_DAT_20                         = IOMUX_PAD(0x664, 0x200, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD20__IPU_DISPB_CS0                            = IOMUX_PAD(0x664, 0x200, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD20__IPU_DISPB_SD_CLK                         = IOMUX_PAD(0x664, 0x200, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD20__ESDHC3_DAT0                              = IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL),
-       MX35_PAD_LD20__GPIO3_26                                 = IOMUX_PAD(0x664, 0x200, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3            = IOMUX_PAD(0x664, 0x200, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD20__ARM11P_TOP_TRACE_13                      = IOMUX_PAD(0x664, 0x200, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD21__IPU_DISPB_DAT_21                         = IOMUX_PAD(0x668, 0x204, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD21__IPU_DISPB_PAR_RS                         = IOMUX_PAD(0x668, 0x204, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD21__IPU_DISPB_SER_RS                         = IOMUX_PAD(0x668, 0x204, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD21__ESDHC3_DAT1                              = IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL),
-       MX35_PAD_LD21__USB_TOP_USBOTG_STP                       = IOMUX_PAD(0x668, 0x204, 4, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD21__GPIO3_27                                 = IOMUX_PAD(0x668, 0x204, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL             = IOMUX_PAD(0x668, 0x204, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD21__ARM11P_TOP_TRACE_14                      = IOMUX_PAD(0x668, 0x204, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD22__IPU_DISPB_DAT_22                         = IOMUX_PAD(0x66c, 0x208, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD22__IPU_DISPB_WR                             = IOMUX_PAD(0x66c, 0x208, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD22__IPU_DISPB_SD_D_I                         = IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL),
-       MX35_PAD_LD22__ESDHC3_DAT2                              = IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL),
-       MX35_PAD_LD22__USB_TOP_USBOTG_NXT                       = IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL),
-       MX35_PAD_LD22__GPIO3_28                                 = IOMUX_PAD(0x66c, 0x208, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR                     = IOMUX_PAD(0x66c, 0x208, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD22__ARM11P_TOP_TRCTL                         = IOMUX_PAD(0x66c, 0x208, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_LD23__IPU_DISPB_DAT_23                         = IOMUX_PAD(0x670, 0x20c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD23__IPU_DISPB_RD                             = IOMUX_PAD(0x670, 0x20c, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD23__IPU_DISPB_SD_D_IO                        = IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL),
-       MX35_PAD_LD23__ESDHC3_DAT3                              = IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL),
-       MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7                    = IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL),
-       MX35_PAD_LD23__GPIO3_29                                 = IOMUX_PAD(0x670, 0x20c, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS                 = IOMUX_PAD(0x670, 0x20c, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_LD23__ARM11P_TOP_TRCLK                         = IOMUX_PAD(0x670, 0x20c, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC                   = IOMUX_PAD(0x674, 0x210, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO                    = IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL),
-       MX35_PAD_D3_HSYNC__GPIO3_30                             = IOMUX_PAD(0x674, 0x210, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE            = IOMUX_PAD(0x674, 0x210, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15                  = IOMUX_PAD(0x674, 0x210, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK                   = IOMUX_PAD(0x678, 0x214, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK                   = IOMUX_PAD(0x678, 0x214, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_FPSHIFT__GPIO3_31                           = IOMUX_PAD(0x678, 0x214, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0      = IOMUX_PAD(0x678, 0x214, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16                = IOMUX_PAD(0x678, 0x214, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY                     = IOMUX_PAD(0x67c, 0x218, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O                      = IOMUX_PAD(0x67c, 0x218, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_DRDY__GPIO1_0                               = IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL),
-       MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1         = IOMUX_PAD(0x67c, 0x218, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17                   = IOMUX_PAD(0x67c, 0x218, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_CONTRAST__IPU_DISPB_CONTR                      = IOMUX_PAD(0x680, 0x21c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CONTRAST__GPIO1_1                              = IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL),
-       MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2        = IOMUX_PAD(0x680, 0x21c, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18                  = IOMUX_PAD(0x680, 0x21c, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC                   = IOMUX_PAD(0x684, 0x220, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_VSYNC__IPU_DISPB_CS1                        = IOMUX_PAD(0x684, 0x220, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_VSYNC__GPIO1_2                              = IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL),
-       MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD                     = IOMUX_PAD(0x684, 0x220, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19                  = IOMUX_PAD(0x684, 0x220, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D3_REV__IPU_DISPB_D3_REV                       = IOMUX_PAD(0x688, 0x224, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_REV__IPU_DISPB_SER_RS                       = IOMUX_PAD(0x688, 0x224, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_REV__GPIO1_3                                = IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL),
-       MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB                     = IOMUX_PAD(0x688, 0x224, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20                    = IOMUX_PAD(0x688, 0x224, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS                       = IOMUX_PAD(0x68c, 0x228, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_CLS__IPU_DISPB_CS2                          = IOMUX_PAD(0x68c, 0x228, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_CLS__GPIO1_4                                = IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL),
-       MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0                = IOMUX_PAD(0x68c, 0x228, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21                    = IOMUX_PAD(0x68c, 0x228, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL                       = IOMUX_PAD(0x690, 0x22c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC                    = IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL),
-       MX35_PAD_D3_SPL__GPIO1_5                                = IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL),
-       MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1                = IOMUX_PAD(0x690, 0x22c, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22                    = IOMUX_PAD(0x690, 0x22c, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD1_CMD__ESDHC1_CMD                            = IOMUX_PAD(0x694, 0x230, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_CMD__MSHC_SCLK                             = IOMUX_PAD(0x694, 0x230, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC                    = IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL),
-       MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4                 = IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL),
-       MX35_PAD_SD1_CMD__GPIO1_6                               = IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL),
-       MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL                      = IOMUX_PAD(0x694, 0x230, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD1_CLK__ESDHC1_CLK                            = IOMUX_PAD(0x698, 0x234, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_CLK__MSHC_BS                               = IOMUX_PAD(0x698, 0x234, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_CLK__IPU_DISPB_BCLK                        = IOMUX_PAD(0x698, 0x234, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5                 = IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL),
-       MX35_PAD_SD1_CLK__GPIO1_7                               = IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL),
-       MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK                      = IOMUX_PAD(0x698, 0x234, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD1_DATA0__ESDHC1_DAT0                         = IOMUX_PAD(0x69c, 0x238, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA0__MSHC_DATA_0                         = IOMUX_PAD(0x69c, 0x238, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA0__IPU_DISPB_CS0                       = IOMUX_PAD(0x69c, 0x238, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6               = IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA0__GPIO1_8                             = IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23                 = IOMUX_PAD(0x69c, 0x238, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD1_DATA1__ESDHC1_DAT1                         = IOMUX_PAD(0x6a0, 0x23c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA1__MSHC_DATA_1                         = IOMUX_PAD(0x6a0, 0x23c, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS                    = IOMUX_PAD(0x6a0, 0x23c, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0               = IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA1__GPIO1_9                             = IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24                 = IOMUX_PAD(0x6a0, 0x23c, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD1_DATA2__ESDHC1_DAT2                         = IOMUX_PAD(0x6a4, 0x240, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA2__MSHC_DATA_2                         = IOMUX_PAD(0x6a4, 0x240, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA2__IPU_DISPB_WR                        = IOMUX_PAD(0x6a4, 0x240, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1               = IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA2__GPIO1_10                            = IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25                 = IOMUX_PAD(0x6a4, 0x240, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD1_DATA3__ESDHC1_DAT3                         = IOMUX_PAD(0x6a8, 0x244, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA3__MSHC_DATA_3                         = IOMUX_PAD(0x6a8, 0x244, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA3__IPU_DISPB_RD                        = IOMUX_PAD(0x6a8, 0x244, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2               = IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA3__GPIO1_11                            = IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL),
-       MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26                 = IOMUX_PAD(0x6a8, 0x244, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD2_CMD__ESDHC2_CMD                            = IOMUX_PAD(0x6ac, 0x248, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD2_CMD__I2C3_SCL                              = IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL),
-       MX35_PAD_SD2_CMD__ESDHC1_DAT4                           = IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL),
-       MX35_PAD_SD2_CMD__IPU_CSI_D_2                           = IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL),
-       MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4                  = IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL),
-       MX35_PAD_SD2_CMD__GPIO2_0                               = IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL),
-       MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1                      = IOMUX_PAD(0x6ac, 0x248, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC                   = IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL),
-
-       MX35_PAD_SD2_CLK__ESDHC2_CLK                            = IOMUX_PAD(0x6b0, 0x24c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD2_CLK__I2C3_SDA                              = IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL),
-       MX35_PAD_SD2_CLK__ESDHC1_DAT5                           = IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL),
-       MX35_PAD_SD2_CLK__IPU_CSI_D_3                           = IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL),
-       MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5                  = IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL),
-       MX35_PAD_SD2_CLK__GPIO2_1                               = IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL),
-       MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1                       = IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL),
-       MX35_PAD_SD2_CLK__IPU_DISPB_CS2                         = IOMUX_PAD(0x6b0, 0x24c, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_SD2_DATA0__ESDHC2_DAT0                         = IOMUX_PAD(0x6b4, 0x250, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA0__UART3_RXD_MUX                       = IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA0__ESDHC1_DAT6                         = IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA0__IPU_CSI_D_4                         = IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6                = IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA0__GPIO2_2                             = IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK                  = IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL),
-
-       MX35_PAD_SD2_DATA1__ESDHC2_DAT1                         = IOMUX_PAD(0x6b8, 0x254, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA1__UART3_TXD_MUX                       = IOMUX_PAD(0x6b8, 0x254, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA1__ESDHC1_DAT7                         = IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA1__IPU_CSI_D_5                         = IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0                = IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA1__GPIO2_3                             = IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL),
-
-       MX35_PAD_SD2_DATA2__ESDHC2_DAT2                         = IOMUX_PAD(0x6bc, 0x258, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA2__UART3_RTS                           = IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA2__CAN1_RXCAN                          = IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA2__IPU_CSI_D_6                         = IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1                = IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA2__GPIO2_4                             = IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL),
-
-       MX35_PAD_SD2_DATA3__ESDHC2_DAT3                         = IOMUX_PAD(0x6c0, 0x25c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA3__UART3_CTS                           = IOMUX_PAD(0x6c0, 0x25c, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA3__CAN1_TXCAN                          = IOMUX_PAD(0x6c0, 0x25c, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA3__IPU_CSI_D_7                         = IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2                = IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL),
-       MX35_PAD_SD2_DATA3__GPIO2_5                             = IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_CS0__ATA_CS0                               = IOMUX_PAD(0x6c4, 0x260, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_CS0__CSPI1_SS3                             = IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_CS0__IPU_DISPB_CS1                         = IOMUX_PAD(0x6c4, 0x260, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_CS0__GPIO2_6                               = IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_CS0__IPU_DIAGB_0                           = IOMUX_PAD(0x6c4, 0x260, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0             = IOMUX_PAD(0x6c4, 0x260, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_CS1__ATA_CS1                               = IOMUX_PAD(0x6c8, 0x264, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_CS1__IPU_DISPB_CS2                         = IOMUX_PAD(0x6c8, 0x264, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_CS1__CSPI2_SS0                             = IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_CS1__GPIO2_7                               = IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_CS1__IPU_DIAGB_1                           = IOMUX_PAD(0x6c8, 0x264, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1             = IOMUX_PAD(0x6c8, 0x264, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DIOR__ATA_DIOR                             = IOMUX_PAD(0x6cc, 0x268, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DIOR__ESDHC3_DAT0                          = IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR                   = IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DIOR__IPU_DISPB_BE0                        = IOMUX_PAD(0x6cc, 0x268, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DIOR__CSPI2_SS1                            = IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DIOR__GPIO2_8                              = IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DIOR__IPU_DIAGB_2                          = IOMUX_PAD(0x6cc, 0x268, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2            = IOMUX_PAD(0x6cc, 0x268, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DIOW__ATA_DIOW                             = IOMUX_PAD(0x6d0, 0x26c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DIOW__ESDHC3_DAT1                          = IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP                   = IOMUX_PAD(0x6d0, 0x26c, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DIOW__IPU_DISPB_BE1                        = IOMUX_PAD(0x6d0, 0x26c, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DIOW__CSPI2_MOSI                           = IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DIOW__GPIO2_9                              = IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DIOW__IPU_DIAGB_3                          = IOMUX_PAD(0x6d0, 0x26c, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3            = IOMUX_PAD(0x6d0, 0x26c, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DMACK__ATA_DMACK                           = IOMUX_PAD(0x6d4, 0x270, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DMACK__ESDHC3_DAT2                         = IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT                  = IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DMACK__CSPI2_MISO                          = IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DMACK__GPIO2_10                            = IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DMACK__IPU_DIAGB_4                         = IOMUX_PAD(0x6d4, 0x270, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0           = IOMUX_PAD(0x6d4, 0x270, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_RESET_B__ATA_RESET_B                       = IOMUX_PAD(0x6d8, 0x274, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_RESET_B__ESDHC3_DAT3                       = IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0             = IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O                  = IOMUX_PAD(0x6d8, 0x274, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_RESET_B__CSPI2_RDY                         = IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_RESET_B__GPIO2_11                          = IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_RESET_B__IPU_DIAGB_5                       = IOMUX_PAD(0x6d8, 0x274, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1         = IOMUX_PAD(0x6d8, 0x274, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_IORDY__ATA_IORDY                           = IOMUX_PAD(0x6dc, 0x278, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_IORDY__ESDHC3_DAT4                         = IOMUX_PAD(0x6dc, 0x278, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1               = IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO                   = IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL),
-       MX35_PAD_ATA_IORDY__ESDHC2_DAT4                         = IOMUX_PAD(0x6dc, 0x278, 4, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_IORDY__GPIO2_12                            = IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_IORDY__IPU_DIAGB_6                         = IOMUX_PAD(0x6dc, 0x278, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2           = IOMUX_PAD(0x6dc, 0x278, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DATA0__ATA_DATA_0                          = IOMUX_PAD(0x6e0, 0x27c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA0__ESDHC3_DAT5                         = IOMUX_PAD(0x6e0, 0x27c, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2               = IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC                 = IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA0__ESDHC2_DAT5                         = IOMUX_PAD(0x6e0, 0x27c, 4, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA0__GPIO2_13                            = IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA0__IPU_DIAGB_7                         = IOMUX_PAD(0x6e0, 0x27c, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3           = IOMUX_PAD(0x6e0, 0x27c, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DATA1__ATA_DATA_1                          = IOMUX_PAD(0x6e4, 0x280, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA1__ESDHC3_DAT6                         = IOMUX_PAD(0x6e4, 0x280, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3               = IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK                    = IOMUX_PAD(0x6e4, 0x280, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA1__ESDHC2_DAT6                         = IOMUX_PAD(0x6e4, 0x280, 4, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA1__GPIO2_14                            = IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA1__IPU_DIAGB_8                         = IOMUX_PAD(0x6e4, 0x280, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27                 = IOMUX_PAD(0x6e4, 0x280, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DATA2__ATA_DATA_2                          = IOMUX_PAD(0x6e8, 0x284, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA2__ESDHC3_DAT7                         = IOMUX_PAD(0x6e8, 0x284, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4               = IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS                    = IOMUX_PAD(0x6e8, 0x284, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA2__ESDHC2_DAT7                         = IOMUX_PAD(0x6e8, 0x284, 4, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA2__GPIO2_15                            = IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA2__IPU_DIAGB_9                         = IOMUX_PAD(0x6e8, 0x284, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28                 = IOMUX_PAD(0x6e8, 0x284, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DATA3__ATA_DATA_3                          = IOMUX_PAD(0x6ec, 0x288, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA3__ESDHC3_CLK                          = IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5               = IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA3__CSPI2_SCLK                          = IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA3__GPIO2_16                            = IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA3__IPU_DIAGB_10                        = IOMUX_PAD(0x6ec, 0x288, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29                 = IOMUX_PAD(0x6ec, 0x288, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DATA4__ATA_DATA_4                          = IOMUX_PAD(0x6f0, 0x28c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA4__ESDHC3_CMD                          = IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6               = IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA4__GPIO2_17                            = IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA4__IPU_DIAGB_11                        = IOMUX_PAD(0x6f0, 0x28c, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30                 = IOMUX_PAD(0x6f0, 0x28c, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DATA5__ATA_DATA_5                          = IOMUX_PAD(0x6f4, 0x290, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7               = IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA5__GPIO2_18                            = IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA5__IPU_DIAGB_12                        = IOMUX_PAD(0x6f4, 0x290, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31                 = IOMUX_PAD(0x6f4, 0x290, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DATA6__ATA_DATA_6                          = IOMUX_PAD(0x6f8, 0x294, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA6__CAN1_TXCAN                          = IOMUX_PAD(0x6f8, 0x294, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA6__UART1_DTR                           = IOMUX_PAD(0x6f8, 0x294, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD                     = IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA6__GPIO2_19                            = IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA6__IPU_DIAGB_13                        = IOMUX_PAD(0x6f8, 0x294, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DATA7__ATA_DATA_7                          = IOMUX_PAD(0x6fc, 0x298, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA7__CAN1_RXCAN                          = IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA7__UART1_DSR                           = IOMUX_PAD(0x6fc, 0x298, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD                     = IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA7__GPIO2_20                            = IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA7__IPU_DIAGB_14                        = IOMUX_PAD(0x6fc, 0x298, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DATA8__ATA_DATA_8                          = IOMUX_PAD(0x700, 0x29c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA8__UART3_RTS                           = IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA8__UART1_RI                            = IOMUX_PAD(0x700, 0x29c, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC                     = IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA8__GPIO2_21                            = IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA8__IPU_DIAGB_15                        = IOMUX_PAD(0x700, 0x29c, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DATA9__ATA_DATA_9                          = IOMUX_PAD(0x704, 0x2a0, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA9__UART3_CTS                           = IOMUX_PAD(0x704, 0x2a0, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA9__UART1_DCD                           = IOMUX_PAD(0x704, 0x2a0, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS                    = IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA9__GPIO2_22                            = IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA9__IPU_DIAGB_16                        = IOMUX_PAD(0x704, 0x2a0, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DATA10__ATA_DATA_10                        = IOMUX_PAD(0x708, 0x2a4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA10__UART3_RXD_MUX                      = IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC                    = IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA10__GPIO2_23                           = IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA10__IPU_DIAGB_17                       = IOMUX_PAD(0x708, 0x2a4, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DATA11__ATA_DATA_11                        = IOMUX_PAD(0x70c, 0x2a8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA11__UART3_TXD_MUX                      = IOMUX_PAD(0x70c, 0x2a8, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS                   = IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA11__GPIO2_24                           = IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA11__IPU_DIAGB_18                       = IOMUX_PAD(0x70c, 0x2a8, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DATA12__ATA_DATA_12                        = IOMUX_PAD(0x710, 0x2ac, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA12__I2C3_SCL                           = IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA12__GPIO2_25                           = IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA12__IPU_DIAGB_19                       = IOMUX_PAD(0x710, 0x2ac, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DATA13__ATA_DATA_13                        = IOMUX_PAD(0x714, 0x2b0, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA13__I2C3_SDA                           = IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA13__GPIO2_26                           = IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA13__IPU_DIAGB_20                       = IOMUX_PAD(0x714, 0x2b0, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DATA14__ATA_DATA_14                        = IOMUX_PAD(0x718, 0x2b4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA14__IPU_CSI_D_0                        = IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA14__KPP_ROW_0                          = IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA14__GPIO2_27                           = IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA14__IPU_DIAGB_21                       = IOMUX_PAD(0x718, 0x2b4, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DATA15__ATA_DATA_15                        = IOMUX_PAD(0x71c, 0x2b8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA15__IPU_CSI_D_1                        = IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA15__KPP_ROW_1                          = IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA15__GPIO2_28                           = IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DATA15__IPU_DIAGB_22                       = IOMUX_PAD(0x71c, 0x2b8, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_INTRQ__ATA_INTRQ                           = IOMUX_PAD(0x720, 0x2bc, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_INTRQ__IPU_CSI_D_2                         = IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL),
-       MX35_PAD_ATA_INTRQ__KPP_ROW_2                           = IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_INTRQ__GPIO2_29                            = IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_INTRQ__IPU_DIAGB_23                        = IOMUX_PAD(0x720, 0x2bc, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN                     = IOMUX_PAD(0x724, 0x2c0, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3                       = IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL),
-       MX35_PAD_ATA_BUFF_EN__KPP_ROW_3                         = IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_BUFF_EN__GPIO2_30                          = IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24                      = IOMUX_PAD(0x724, 0x2c0, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DMARQ__ATA_DMARQ                           = IOMUX_PAD(0x728, 0x2c4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DMARQ__IPU_CSI_D_4                         = IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DMARQ__KPP_COL_0                           = IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DMARQ__GPIO2_31                            = IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DMARQ__IPU_DIAGB_25                        = IOMUX_PAD(0x728, 0x2c4, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4                  = IOMUX_PAD(0x728, 0x2c4, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DA0__ATA_DA_0                              = IOMUX_PAD(0x72c, 0x2c8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DA0__IPU_CSI_D_5                           = IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DA0__KPP_COL_1                             = IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DA0__GPIO3_0                               = IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL),
-       MX35_PAD_ATA_DA0__IPU_DIAGB_26                          = IOMUX_PAD(0x72c, 0x2c8, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5                    = IOMUX_PAD(0x72c, 0x2c8, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DA1__ATA_DA_1                              = IOMUX_PAD(0x730, 0x2cc, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DA1__IPU_CSI_D_6                           = IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DA1__KPP_COL_2                             = IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DA1__GPIO3_1                               = IOMUX_PAD(0x730, 0x2cc, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DA1__IPU_DIAGB_27                          = IOMUX_PAD(0x730, 0x2cc, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6                    = IOMUX_PAD(0x730, 0x2cc, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_ATA_DA2__ATA_DA_2                              = IOMUX_PAD(0x734, 0x2d0, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DA2__IPU_CSI_D_7                           = IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DA2__KPP_COL_3                             = IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL),
-       MX35_PAD_ATA_DA2__GPIO3_2                               = IOMUX_PAD(0x734, 0x2d0, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DA2__IPU_DIAGB_28                          = IOMUX_PAD(0x734, 0x2d0, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7                    = IOMUX_PAD(0x734, 0x2d0, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_MLB_CLK__MLB_MLBCLK                            = IOMUX_PAD(0x738, 0x2d4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_MLB_CLK__GPIO3_3                               = IOMUX_PAD(0x738, 0x2d4, 5, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_MLB_DAT__MLB_MLBDAT                            = IOMUX_PAD(0x73c, 0x2d8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_MLB_DAT__GPIO3_4                               = IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL),
-
-       MX35_PAD_MLB_SIG__MLB_MLBSIG                            = IOMUX_PAD(0x740, 0x2dc, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_MLB_SIG__GPIO3_5                               = IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_TX_CLK__FEC_TX_CLK                         = IOMUX_PAD(0x744, 0x2e0, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4                        = IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX                      = IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR                  = IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_CLK__CSPI2_MOSI                         = IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_CLK__GPIO3_6                            = IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC                = IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0               = IOMUX_PAD(0x744, 0x2e0, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_RX_CLK__FEC_RX_CLK                         = IOMUX_PAD(0x748, 0x2e4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5                        = IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX                      = IOMUX_PAD(0x748, 0x2e4, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP                  = IOMUX_PAD(0x748, 0x2e4, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_CLK__CSPI2_MISO                         = IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_CLK__GPIO3_7                            = IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I                   = IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1               = IOMUX_PAD(0x748, 0x2e4, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_RX_DV__FEC_RX_DV                           = IOMUX_PAD(0x74c, 0x2e8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_DV__ESDHC1_DAT6                         = IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_DV__UART3_RTS                           = IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT                   = IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_DV__CSPI2_SCLK                          = IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_DV__GPIO3_8                             = IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK                    = IOMUX_PAD(0x74c, 0x2e8, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2                = IOMUX_PAD(0x74c, 0x2e8, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_COL__FEC_COL                               = IOMUX_PAD(0x750, 0x2ec, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_COL__ESDHC1_DAT7                           = IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_COL__UART3_CTS                             = IOMUX_PAD(0x750, 0x2ec, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0                  = IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_COL__CSPI2_RDY                             = IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL),
-       MX35_PAD_FEC_COL__GPIO3_9                               = IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_COL__IPU_DISPB_SER_RS                      = IOMUX_PAD(0x750, 0x2ec, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3                  = IOMUX_PAD(0x750, 0x2ec, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_RDATA0__FEC_RDATA_0                        = IOMUX_PAD(0x754, 0x2f0, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA0__PWM_PWMO                           = IOMUX_PAD(0x754, 0x2f0, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA0__UART3_DTR                          = IOMUX_PAD(0x754, 0x2f0, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1               = IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA0__CSPI2_SS0                          = IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA0__GPIO3_10                           = IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1                      = IOMUX_PAD(0x754, 0x2f0, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4               = IOMUX_PAD(0x754, 0x2f0, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_TDATA0__FEC_TDATA_0                        = IOMUX_PAD(0x758, 0x2f4, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1                   = IOMUX_PAD(0x758, 0x2f4, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA0__UART3_DSR                          = IOMUX_PAD(0x758, 0x2f4, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2               = IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA0__CSPI2_SS1                          = IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA0__GPIO3_11                           = IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0                      = IOMUX_PAD(0x758, 0x2f4, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5               = IOMUX_PAD(0x758, 0x2f4, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_TX_EN__FEC_TX_EN                           = IOMUX_PAD(0x75c, 0x2f8, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1                     = IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_EN__UART3_RI                            = IOMUX_PAD(0x75c, 0x2f8, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3                = IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_EN__GPIO3_12                            = IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS                    = IOMUX_PAD(0x75c, 0x2f8, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6                = IOMUX_PAD(0x75c, 0x2f8, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_MDC__FEC_MDC                               = IOMUX_PAD(0x760, 0x2fc, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_MDC__CAN2_TXCAN                            = IOMUX_PAD(0x760, 0x2fc, 1, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_MDC__UART3_DCD                             = IOMUX_PAD(0x760, 0x2fc, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4                  = IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_MDC__GPIO3_13                              = IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_MDC__IPU_DISPB_WR                          = IOMUX_PAD(0x760, 0x2fc, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7                  = IOMUX_PAD(0x760, 0x2fc, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_MDIO__FEC_MDIO                             = IOMUX_PAD(0x764, 0x300, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_MDIO__CAN2_RXCAN                           = IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL),
-       MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5                 = IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_MDIO__GPIO3_14                             = IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_MDIO__IPU_DISPB_RD                         = IOMUX_PAD(0x764, 0x300, 6, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8                 = IOMUX_PAD(0x764, 0x300, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_TX_ERR__FEC_TX_ERR                         = IOMUX_PAD(0x768, 0x304, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_ERR__OWIRE_LINE                         = IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK                 = IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6               = IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_ERR__GPIO3_15                           = IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC                 = IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL),
-       MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9               = IOMUX_PAD(0x768, 0x304, 7, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_RX_ERR__FEC_RX_ERR                         = IOMUX_PAD(0x76c, 0x308, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0                        = IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7               = IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_ERR__KPP_COL_4                          = IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_ERR__GPIO3_16                           = IOMUX_PAD(0x76c, 0x308, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO                  = IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_CRS__FEC_CRS                               = IOMUX_PAD(0x770, 0x30c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_CRS__IPU_CSI_D_1                           = IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL),
-       MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR                     = IOMUX_PAD(0x770, 0x30c, 3, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_CRS__KPP_COL_5                             = IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_CRS__GPIO3_17                              = IOMUX_PAD(0x770, 0x30c, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_CRS__IPU_FLASH_STROBE                      = IOMUX_PAD(0x770, 0x30c, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_RDATA1__FEC_RDATA_1                        = IOMUX_PAD(0x774, 0x310, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA1__IPU_CSI_D_2                        = IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC                    = IOMUX_PAD(0x774, 0x310, 2, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC                   = IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA1__KPP_COL_6                          = IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA1__GPIO3_18                           = IOMUX_PAD(0x774, 0x310, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0                      = IOMUX_PAD(0x774, 0x310, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_TDATA1__FEC_TDATA_1                        = IOMUX_PAD(0x778, 0x314, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA1__IPU_CSI_D_3                        = IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS                   = IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA1__KPP_COL_7                          = IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA1__GPIO3_19                           = IOMUX_PAD(0x778, 0x314, 5, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1                      = IOMUX_PAD(0x778, 0x314, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_RDATA2__FEC_RDATA_2                        = IOMUX_PAD(0x77c, 0x318, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA2__IPU_CSI_D_4                        = IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD                    = IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA2__KPP_ROW_4                          = IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA2__GPIO3_20                           = IOMUX_PAD(0x77c, 0x318, 5, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_TDATA2__FEC_TDATA_2                        = IOMUX_PAD(0x780, 0x31c, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA2__IPU_CSI_D_5                        = IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD                    = IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA2__KPP_ROW_5                          = IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA2__GPIO3_21                           = IOMUX_PAD(0x780, 0x31c, 5, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_RDATA3__FEC_RDATA_3                        = IOMUX_PAD(0x784, 0x320, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA3__IPU_CSI_D_6                        = IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC                    = IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA3__KPP_ROW_6                          = IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_RDATA3__GPIO3_22                           = IOMUX_PAD(0x784, 0x320, 6, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_FEC_TDATA3__FEC_TDATA_3                        = IOMUX_PAD(0x788, 0x324, 0, 0x0,   0, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA3__IPU_CSI_D_7                        = IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS                   = IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA3__KPP_ROW_7                          = IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL),
-       MX35_PAD_FEC_TDATA3__GPIO3_23                           = IOMUX_PAD(0x788, 0x324, 5, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK                     = IOMUX_PAD(0x78c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-
-       MX35_PAD_TEST_MODE__TCU_TEST_MODE                       = IOMUX_PAD(0x790, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
-};
-
-#endif /* __IOMUX_MX35_H__ */

diff --git a/arch/arm/include/asm/arch-mx35/lowlevel_macro.S b/arch/arm/include/asm/arch-mx35/lowlevel_macro.S
deleted file mode 100644 (file)
index 4b1c9f8..0000000
--- a/arch/arm/include/asm/arch-mx35/lowlevel_macro.S
+++ /dev/null
@@ -1,125 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- */
-
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-#include <asm/macro.h>
-
-/*
- * AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.
- *
- * Default argument values:
- *  - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
- *    user-mode.
- *  - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for
- *    SDMA to access them.
- */
-.macro init_aips mpr=0x77777777, opacr=0x00000000
-       ldr     r0, =AIPS1_BASE_ADDR
-       ldr     r1, =\mpr
-       str     r1, [r0, #AIPS_MPR_0_7]
-       str     r1, [r0, #AIPS_MPR_8_15]
-       ldr     r2, =AIPS2_BASE_ADDR
-       str     r1, [r2, #AIPS_MPR_0_7]
-       str     r1, [r2, #AIPS_MPR_8_15]
-
-       /* Did not change the AIPS control registers access type. */
-       ldr     r1, =\opacr
-       str     r1, [r0, #AIPS_OPACR_0_7]
-       str     r1, [r0, #AIPS_OPACR_8_15]
-       str     r1, [r0, #AIPS_OPACR_16_23]
-       str     r1, [r0, #AIPS_OPACR_24_31]
-       str     r1, [r0, #AIPS_OPACR_32_39]
-       str     r1, [r2, #AIPS_OPACR_0_7]
-       str     r1, [r2, #AIPS_OPACR_8_15]
-       str     r1, [r2, #AIPS_OPACR_16_23]
-       str     r1, [r2, #AIPS_OPACR_24_31]
-       str     r1, [r2, #AIPS_OPACR_32_39]
-.endm
-
-/*
- * MAX (Multi-Layer AHB Crossbar Switch) setup
- *
- * Default argument values:
- *  - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1
- *  - SGPCR: always park on last master
- *  - MGPCR: restore default values
- */
-.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000
-       ldr     r0, =MAX_BASE_ADDR
-       ldr     r1, =\mpr
-       str     r1, [r0, #MAX_MPR0]     /* for S0 */
-       str     r1, [r0, #MAX_MPR1]     /* for S1 */
-       str     r1, [r0, #MAX_MPR2]     /* for S2 */
-       str     r1, [r0, #MAX_MPR3]     /* for S3 */
-       str     r1, [r0, #MAX_MPR4]     /* for S4 */
-       ldr     r1, =\sgpcr
-       str     r1, [r0, #MAX_SGPCR0]   /* for S0 */
-       str     r1, [r0, #MAX_SGPCR1]   /* for S1 */
-       str     r1, [r0, #MAX_SGPCR2]   /* for S2 */
-       str     r1, [r0, #MAX_SGPCR3]   /* for S3 */
-       str     r1, [r0, #MAX_SGPCR4]   /* for S4 */
-       ldr     r1, =\mgpcr
-       str     r1, [r0, #MAX_MGPCR0]   /* for M0 */
-       str     r1, [r0, #MAX_MGPCR1]   /* for M1 */
-       str     r1, [r0, #MAX_MGPCR2]   /* for M2 */
-       str     r1, [r0, #MAX_MGPCR3]   /* for M3 */
-       str     r1, [r0, #MAX_MGPCR4]   /* for M4 */
-       str     r1, [r0, #MAX_MGPCR5]   /* for M5 */
-.endm
-
-/*
- * M3IF setup
- *
- * Default argument values:
- *  - CTL:
- * MRRP[0] = L2CC0 not on priority list (0 << 0)       = 0x00000000
- * MRRP[1] = L2CC1 not on priority list (0 << 1)       = 0x00000000
- * MRRP[2] = MBX not on priority list (0 << 2)         = 0x00000000
- * MRRP[3] = MAX1 not on priority list (0 << 3)                = 0x00000000
- * MRRP[4] = SDMA not on priority list (0 << 4)                = 0x00000000
- * MRRP[5] = MPEG4 not on priority list (0 << 5)       = 0x00000000
- * MRRP[6] = IPU1 on priority list (1 << 6)            = 0x00000040
- * MRRP[7] = IPU2 not on priority list (0 << 7)                = 0x00000000
- *                                                     ------------
- *                                                       0x00000040
- */
-.macro init_m3if ctl=0x00000040
-       /* M3IF Control Register (M3IFCTL) */
-       write32 M3IF_BASE_ADDR, \ctl
-.endm
-
-.macro core_init
-       mrc     p15, 0, r1, c1, c0, 0
-
-       /* Set branch prediction enable */
-       mrc     p15, 0, r0, c1, c0, 1
-       orr     r0, r0, #7
-       mcr     p15, 0, r0, c1, c0, 1
-       orr     r1, r1, #1 << 11
-
-       /* Set unaligned access enable */
-       orr     r1, r1, #1 << 22
-
-       /* Set low int latency enable */
-       orr     r1, r1, #1 << 21
-
-       mcr     p15, 0, r1, c1, c0, 0
-
-       mov     r0, #0
-
-       mcr     p15, 0, r0, c15, c2, 4
-
-       mcr     p15, 0, r0, c7, c7, 0   /* Invalidate I cache and D cache */
-       mcr     p15, 0, r0, c8, c7, 0   /* Invalidate TLBs */
-       mcr     p15, 0, r0, c7, c10, 4  /* Drain the write buffer */
-
-       /* Setup the Peripheral Port Memory Remap Register */
-       ldr     r0, =0x40000015         /* Start from AIPS 2-GB region */
-       mcr     p15, 0, r0, c15, c2, 4
-.endm

diff --git a/arch/arm/include/asm/arch-mx35/mmc_host_def.h b/arch/arm/include/asm/arch-mx35/mmc_host_def.h
deleted file mode 100644 (file)
index 81c19bb..0000000
--- a/arch/arm/include/asm/arch-mx35/mmc_host_def.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- */
-
-#ifndef MMC_HOST_DEF_H
-#define MMC_HOST_DEF_H
-
-/* Driver definitions */
-#define MMCSD_SECTOR_SIZE              512
-
-#endif /* MMC_HOST_DEF_H */

diff --git a/arch/arm/include/asm/arch-mx35/sys_proto.h b/arch/arm/include/asm/arch-mx35/sys_proto.h
deleted file mode 100644 (file)
index 6e8b841..0000000
--- a/arch/arm/include/asm/arch-mx35/sys_proto.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- */
-
-#ifndef _MX35_SYS_PROTO_H_
-#define _MX35_SYS_PROTO_H_
-
-#include <asm/mach-imx/sys_proto.h>
-
-void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, u32 row,
-                         u32 col, u32 dsize, u32 refresh);
-
-#endif

diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c
index 1a306ec4153b8a333fd7ce9a0061e98fc991ba74..379f77a45d9d4b17d7914440cf2cc9951610963c 100644 (file)
--- a/arch/arm/lib/asm-offsets.c
+++ b/arch/arm/lib/asm-offsets.c
@@ -15,7 +15,7 @@
 #include <linux/kbuild.h>
 #include <linux/arm-smccc.h>
 
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) \
        || defined(CONFIG_MX51) || defined(CONFIG_MX53)
 #include <asm/arch/imx-regs.h>
 #endif
@@ -97,56 +97,6 @@ int main(void)
                offsetof(struct system_control_regs, fmcr));
 #endif
 
-#if defined(CONFIG_MX35)
-       /* Round up to make sure size gives nice stack alignment */
-       DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
-       DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
-       DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
-       DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
-       DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
-       DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
-       DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
-       DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
-       DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
-       DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
-       DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
-       DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
-       DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
-       DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
-       DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
-
-       /* Multi-Layer AHB Crossbar Switch */
-       DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
-       DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
-       DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
-       DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
-       DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
-       DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
-       DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
-       DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
-       DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
-       DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
-       DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
-       DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
-       DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
-       DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
-       DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
-       DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
-
-       /* AHB <-> IP-Bus Interface */
-       DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
-       DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
-       DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
-       DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
-       DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
-       DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
-       DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
-       DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
-       DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
-       DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
-       DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
-#endif
-
 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
        /* Round up to make sure size gives nice stack alignment */
        DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));

diff --git a/board/CarMediaLab/flea3/Kconfig b/board/CarMediaLab/flea3/Kconfig
deleted file mode 100644 (file)
index 7113f2b..0000000
--- a/board/CarMediaLab/flea3/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_FLEA3
-
-config SYS_BOARD
-       default "flea3"
-
-config SYS_VENDOR
-       default "CarMediaLab"
-
-config SYS_SOC
-       default "mx35"
-
-config SYS_CONFIG_NAME
-       default "flea3"
-
-endif

diff --git a/board/CarMediaLab/flea3/MAINTAINERS b/board/CarMediaLab/flea3/MAINTAINERS
deleted file mode 100644 (file)
index c7b0df7..0000000
--- a/board/CarMediaLab/flea3/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-FLEA3 BOARD
-M:     Stefano Babic <sbabic@denx.de>
-S:     Maintained
-F:     board/CarMediaLab/flea3/
-F:     include/configs/flea3.h
-F:     configs/flea3_defconfig

diff --git a/board/CarMediaLab/flea3/Makefile b/board/CarMediaLab/flea3/Makefile
deleted file mode 100644 (file)
index edaac86..0000000
--- a/board/CarMediaLab/flea3/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-
-obj-y  := flea3.o
-obj-y  += lowlevel_init.o

diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c
deleted file mode 100644 (file)
index ecd70ec..0000000
--- a/board/CarMediaLab/flea3/flea3.c
+++ /dev/null
@@ -1,227 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <env.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/iomux-mx35.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <asm/gpio.h>
-#include <asm/arch/sys_proto.h>
-#include <netdev.h>
-#include <fdt_support.h>
-#include <mtd_node.h>
-#include <jffs2/load_kernel.h>
-
-#ifndef CONFIG_BOARD_EARLY_INIT_F
-#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
-#endif
-
-#define CCM_CCMR_CONFIG                0x003F4208
-
-#define ESDCTL_DDR2_CONFIG     0x007FFC3F
-
-static inline void dram_wait(unsigned int count)
-{
-       volatile unsigned int wait = count;
-
-       while (wait--)
-               ;
-}
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
-       gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
-               PHYS_SDRAM_1_SIZE);
-
-       return 0;
-}
-
-static void board_setup_sdram(void)
-{
-       struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
-
-       /* Initialize with default values both CSD0/1 */
-       writel(0x2000, &esdc->esdctl0);
-       writel(0x2000, &esdc->esdctl1);
-
-
-       mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
-                            13, 10, 2, 0x8080);
-}
-
-static void setup_iomux_uart3(void)
-{
-       static const iomux_v3_cfg_t uart3_pads[] = {
-               MX35_PAD_RTS2__UART3_RXD_MUX,
-               MX35_PAD_CTS2__UART3_TXD_MUX,
-       };
-
-       imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
-}
-
-#define I2C_PAD_CTRL   (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
-
-static void setup_iomux_i2c(void)
-{
-       static const iomux_v3_cfg_t i2c_pads[] = {
-               NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
-               NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
-
-               NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
-               NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
-       };
-
-       imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
-}
-
-
-static void setup_iomux_spi(void)
-{
-       static const iomux_v3_cfg_t spi_pads[] = {
-               MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
-               MX35_PAD_CSPI1_MISO__CSPI1_MISO,
-               MX35_PAD_CSPI1_SS0__CSPI1_SS0,
-               MX35_PAD_CSPI1_SS1__CSPI1_SS1,
-               MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
-       };
-
-       imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
-}
-
-static void setup_iomux_fec(void)
-{
-       static const iomux_v3_cfg_t fec_pads[] = {
-               MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
-               MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
-               MX35_PAD_FEC_RX_DV__FEC_RX_DV,
-               MX35_PAD_FEC_COL__FEC_COL,
-               MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
-               MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
-               MX35_PAD_FEC_TX_EN__FEC_TX_EN,
-               MX35_PAD_FEC_MDC__FEC_MDC,
-               MX35_PAD_FEC_MDIO__FEC_MDIO,
-               MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
-               MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
-               MX35_PAD_FEC_CRS__FEC_CRS,
-               MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
-               MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
-               MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
-               MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
-               MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
-               MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
-               /* GPIO used to power off ethernet */
-               MX35_PAD_STXFS4__GPIO2_31,
-       };
-
-       /* setup pins for FEC */
-       imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
-int board_early_init_f(void)
-{
-       struct ccm_regs *ccm =
-               (struct ccm_regs *)IMX_CCM_BASE;
-
-       /* setup GPIO3_1 to set HighVCore signal */
-       imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
-       gpio_direction_output(65, 1);
-
-       /* initialize PLL and clock configuration */
-       writel(CCM_CCMR_CONFIG, &ccm->ccmr);
-
-       writel(CCM_MPLL_532_HZ, &ccm->mpctl);
-       writel(CCM_PPLL_300_HZ, &ccm->ppctl);
-
-       /* Set the core to run at 532 Mhz */
-       writel(0x00001000, &ccm->pdr0);
-
-       /* Set-up RAM */
-       board_setup_sdram();
-
-       /* enable clocks */
-       writel(readl(&ccm->cgr0) |
-               MXC_CCM_CGR0_EMI_MASK |
-               MXC_CCM_CGR0_EDIO_MASK |
-               MXC_CCM_CGR0_EPIT1_MASK,
-               &ccm->cgr0);
-
-       writel(readl(&ccm->cgr1) |
-               MXC_CCM_CGR1_FEC_MASK |
-               MXC_CCM_CGR1_GPIO1_MASK |
-               MXC_CCM_CGR1_GPIO2_MASK |
-               MXC_CCM_CGR1_GPIO3_MASK |
-               MXC_CCM_CGR1_I2C1_MASK |
-               MXC_CCM_CGR1_I2C2_MASK |
-               MXC_CCM_CGR1_I2C3_MASK,
-               &ccm->cgr1);
-
-       /* Set-up NAND */
-       __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
-
-       /* Set pinmux for the required peripherals */
-       setup_iomux_uart3();
-       setup_iomux_i2c();
-       setup_iomux_fec();
-       setup_iomux_spi();
-
-       return 0;
-}
-
-int board_init(void)
-{
-       /* address of boot parameters */
-       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-       /* Enable power for ethernet */
-       gpio_direction_output(63, 0);
-
-       udelay(2000);
-
-       return 0;
-}
-
-#ifdef CONFIG_REVISION_TAG
-u32 get_board_rev(void)
-{
-       int rev = 0;
-
-       return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
-}
-#endif
-
-/*
- * called prior to booting kernel or by 'fdt boardsetup' command
- *
- */
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-       static const struct node_info nodes[] = {
-               { "physmap-flash.0", MTD_DEV_TYPE_NOR, },  /* NOR flash */
-               { "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
-       };
-
-       if (env_get("fdt_noauto")) {
-               puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
-               return 0;
-       }
-
-       fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-
-       return 0;
-}

diff --git a/board/CarMediaLab/flea3/lowlevel_init.S b/board/CarMediaLab/flea3/lowlevel_init.S
deleted file mode 100644 (file)
index 8186b39..0000000
--- a/board/CarMediaLab/flea3/lowlevel_init.S
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
- */
-
-#include <config.h>
-#include <asm/arch/lowlevel_macro.S>
-
-.globl lowlevel_init
-lowlevel_init:
-
-       core_init
-
-       init_aips
-
-       init_max
-
-       init_m3if
-
-       mov pc, lr

diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig
deleted file mode 100644 (file)
index 81e291a..0000000
--- a/configs/flea3_defconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_TARGET_FLEA3=y
-CONFIG_SYS_TEXT_BASE=0xA0000000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
-CONFIG_SYS_MALLOC_LEN=0x110000
-CONFIG_SYS_LOAD_ADDR=0x80800000
-CONFIG_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="flea3 U-Boot > "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:50m(root1),32m(rootfb),64m(pcache),64m(app1),10m(app2),-(spool);physmap-flash.0:512k(u-boot),64k(env1),64k(env2),3776k(kernel1),3776k(kernel2)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xA0080000
-CONFIG_ENV_ADDR_REDUND=0xA0090000
-CONFIG_MXC_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_MXC=y
-CONFIG_SYS_MXC_I2C3_SLAVE=0xfe
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_MXC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ8XXX=y
-CONFIG_MII=y
-CONFIG_MXC_UART=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y

diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c
index 59cef205754b58726aa5f4d1467cb4445953d335..d6e17bfeaeb34fa98809a34ab1cacf7f6128ea52 100644 (file)
--- a/drivers/mtd/nand/raw/mxc_nand.c
+++ b/drivers/mtd/nand/raw/mxc_nand.c
@@ -11,7 +11,7 @@
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <asm/io.h>
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || \
        defined(CONFIG_MX51) || defined(CONFIG_MX53)
 #include <asm/arch/imx-regs.h>
 #endif

diff --git a/drivers/mtd/nand/raw/mxc_nand.h b/drivers/mtd/nand/raw/mxc_nand.h
index 1c7f3a2e227d808628a16e90db02b167efa1bb18..09bcb8f028a06af359408de200cc4dca70c82c3b 100644 (file)
--- a/drivers/mtd/nand/raw/mxc_nand.h
+++ b/drivers/mtd/nand/raw/mxc_nand.h
@@ -29,7 +29,7 @@
 #define is_mxc_nfc_1()         1
 #define is_mxc_nfc_21()                0
 #define is_mxc_nfc_32()                0
-#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
+#elif defined(CONFIG_MX25)
 #define MXC_NFC_V2_1
 #define is_mxc_nfc_1()         0
 #define is_mxc_nfc_21()                1

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 36ee43210a9fa6c7335f9cfdb8d161cd96fb92d8..cbea165b9d543fe9b0ea37d52ac9885ff6bce948 100644 (file)
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -645,8 +645,7 @@ config MCFUART
 
 config MXC_UART
        bool "IMX serial port support"
-       depends on ARCH_MX25 || ARCH_MX31 || TARGET_FLEA3 \
-               || MX5 || MX6 || MX7 || IMX8M
+       depends on ARCH_MX25 || ARCH_MX31 || MX5 || MX6 || MX7 || IMX8M
        help
          If you have a machine based on a Motorola IMX CPU you
          can enable its onboard serial port by enabling this option.

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index a80c3e737dbd32ff4a96fd7e9f07b8d1805db618..d9a79a20318a29031b1740dc5aa66db5734f2d73 100644 (file)
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -23,7 +23,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* MX35 and older is CSPI */
-#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX31)
 #define MXC_CSPI
 struct cspi_regs {
        u32 rxdata;
@@ -48,7 +48,7 @@ struct cspi_regs {
 #define MXC_CSPICTRL_RXOVF             BIT(6)
 #define MXC_CSPIPERIOD_32KHZ           BIT(15)
 #define MAX_SPI_BYTES                  4
-#if defined(CONFIG_MX25) || defined(CONFIG_MX35)
+#if defined(CONFIG_MX25)
 #define MXC_CSPICTRL_CHIPSELECT(x)     (((x) & 0x3) << 12)
 #define MXC_CSPICTRL_BITCOUNT(x)       (((x) & 0xfff) << 20)
 #define MXC_CSPICTRL_TC                        BIT(7)
@@ -211,9 +211,6 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
                MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
                MXC_CSPICTRL_DATARATE(div) |
                MXC_CSPICTRL_EN |
-#ifdef CONFIG_MX35
-               MXC_CSPICTRL_SSCTL |
-#endif
                MXC_CSPICTRL_MODE;
 
        if (mode & SPI_CPHA)

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index d0b7ac512e804783e5e11ed9f7f514693b38e01e..090548fb196423caa7e377cde95ebfdee0df9a1f 100644 (file)
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -147,55 +147,6 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
                if (!(flags & MXC_EHCI_TTL_ENABLED))
                        v |= MX31_H2_DT_BIT;
 
-               break;
-       default:
-               return -EINVAL;
-       }
-#elif defined(CONFIG_MX35)
-       switch (port) {
-       case 0: /* OTG port */
-               v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
-                               MX35_OTG_OCPOL_BIT);
-               v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
-
-               if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                       v |= MX35_OTG_PM_BIT;
-
-               if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-                       v |= MX35_OTG_PP_BIT;
-
-               if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
-                       v |= MX35_OTG_OCPOL_BIT;
-
-               break;
-       case 1: /* H1 port */
-               v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
-                               MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT |
-                               MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT |
-                               MX35_H1_IPPUE_UP_BIT);
-               v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
-
-               if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-                       v |= MX35_H1_PM_BIT;
-
-               if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-                       v |= MX35_H1_PP_BIT;
-
-               if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
-                       v |= MX35_H1_OCPOL_BIT;
-
-               if (!(flags & MXC_EHCI_TTL_ENABLED))
-                       v |= MX35_H1_TLL_BIT;
-
-               if (flags & MXC_EHCI_INTERNAL_PHY)
-                       v |= MX35_H1_USBTE_BIT;
-
-               if (flags & MXC_EHCI_IPPUE_DOWN)
-                       v |= MX35_H1_IPPUE_DOWN_BIT;
-
-               if (flags & MXC_EHCI_IPPUE_UP)
-                       v |= MX35_H1_IPPUE_UP_BIT;
-
                break;
        default:
                return -EINVAL;
@@ -230,10 +181,6 @@ int ehci_hcd_init(int index, enum usb_init_type init,
        setbits_le32(&ehci->usbmode, CM_HOST);
        __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
        mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
-#ifdef CONFIG_MX35
-       /* Workaround for ENGcm11601 */
-       __raw_writel(0, &ehci->sbuscfg);
-#endif
 
        udelay(10000);
 

diff --git a/include/configs/flea3.h b/include/configs/flea3.h
deleted file mode 100644 (file)
index 6c3b2c4..0000000
--- a/include/configs/flea3.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
- *
- * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
- *
- * Configuration for the flea3 board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
- /* High Level Configuration Options */
-#define CONFIG_MX35
-
-/* Set TEXT at the beginning of the NOR flash */
-
-/* This is required to setup the ESDC controller */
-
-/*
- * Hardware drivers
- */
-#define CONFIG_SYS_SPD_BUS_NUM         2 /* I2C3 */
-
-/*
- * UART (console)
- */
-#define CONFIG_MXC_UART_BASE   UART3_BASE
-
-/*
- * Command definition
- */
-
-#define CONFIG_NET_RETRY_COUNT 100
-
-/*
- * Ethernet on SOC (FEC)
- */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE   FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x1
-
-#define CONFIG_ARP_TIMEOUT     200UL
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_CBSIZE      512     /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS     32      /* max number of command args */
-
-/*
- * Physical Memory Map
- */
-#define PHYS_SDRAM_1           CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE      (128 * 1024 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE          CSD0_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR       (IRAM_BASE_ADDR + 0x10000)
-#define CONFIG_SYS_INIT_RAM_SIZE               (IRAM_SIZE / 2)
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - \
-                                       GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_INIT_RAM_ADDR + \
-                                       CONFIG_SYS_GBL_DATA_OFFSET)
-
-/*
- * MTD Command for mtdparts
- */
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE          CS0_BASE_ADDR
-#define CONFIG_SYS_MAX_FLASH_BANKS 1   /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512  /* max number of sectors on one chip */
-/* Monitor at beginning of flash */
-#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN         (512 * 1024)
-
-/* Address and size of Redundant Environment Sector    */
-
-/*
- * CFI FLASH driver setup
- */
-
-/* A non-standard buffered write algorithm */
-
-/*
- * NAND FLASH driver setup
- */
-#define CONFIG_MXC_NAND_REGS_BASE      (NFC_BASE_ADDR)
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_SYS_NAND_BASE           (NFC_BASE_ADDR)
-#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_LARGEPAGE
-
-/*
- * Default environment and default scripts
- * to update uboot and load kernel
- */
-
-#define CONFIG_HOSTNAME "flea3"
-#define        CONFIG_EXTRA_ENV_SETTINGS                                       \
-       "netdev=eth0\0"                                                 \
-       "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
-               "nfsroot=${serverip}:${rootpath}\0"                     \
-       "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
-       "addip_sta=setenv bootargs ${bootargs} "                        \
-               "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
-               ":${hostname}:${netdev}:off panic=1\0"                  \
-       "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"               \
-       "addip=if test -n ${ipdyn};then run addip_dyn;"                 \
-               "else run addip_sta;fi\0"                               \
-       "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
-       "addtty=setenv bootargs ${bootargs}"                            \
-               " console=ttymxc2,${baudrate}\0"                        \
-       "addmisc=setenv bootargs ${bootargs} ${misc}\0"                 \
-       "loadaddr=80800000\0"                                           \
-       "kernel_addr_r=80800000\0"                                      \
-       "hostname=" CONFIG_HOSTNAME "\0"                        \
-       "bootfile=" CONFIG_HOSTNAME "/uImage\0"         \
-       "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0"   \
-       "flash_self=run ramargs addip addtty addmtd addmisc;"           \
-               "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
-       "flash_nfs=run nfsargs addip addtty addmtd addmisc;"            \
-               "bootm ${kernel_addr}\0"                                \
-       "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
-               "run nfsargs addip addtty addmtd addmisc;"              \
-               "bootm ${kernel_addr_r}\0"                              \
-       "net_self_load=tftp ${kernel_addr_r} ${bootfile};"              \
-               "tftp ${ramdisk_addr_r} ${ramdisk_file};\0"             \
-       "net_self=if run net_self_load;then "                           \
-               "run ramargs addip addtty addmtd addmisc;"              \
-               "bootm ${kernel_addr_r} ${ramdisk_addr_r};"             \
-               "else echo Images not loades;fi\0"                      \
-       "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"               \
-       "load=tftp ${loadaddr} ${u-boot}\0"                             \
-       "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0"         \
-       "update=protect off ${uboot_addr} +80000;"                      \
-               "erase ${uboot_addr} +80000;"                           \
-               "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"          \
-       "upd=if run load;then echo Updating u-boot;if run update;"      \
-               "then echo U-Boot updated;"                             \
-                       "else echo Error updating u-boot !;"            \
-                       "echo Board without bootloader !!;"             \
-               "fi;"                                                   \
-               "else echo U-Boot not downloaded..exiting;fi\0"         \
-       "bootcmd=run net_nfs\0"
-
-#endif                         /* __CONFIG_H */