{
struct mscc_miim_dev *miim = bus->priv;
int offset = miim->phy_reset_offset;
+ int reset_bits = PHY_CFG_PHY_ENA | PHY_CFG_PHY_COMMON_RESET |
+ PHY_CFG_PHY_RESET;
int ret;
if (miim->phy_regs) {
- ret = regmap_write(miim->phy_regs,
- MSCC_PHY_REG_PHY_CFG + offset, 0);
+ ret = regmap_write(miim->phy_regs, offset, 0);
if (ret < 0) {
WARN_ONCE(1, "mscc reset set error %d\n", ret);
return ret;
}
- ret = regmap_write(miim->phy_regs,
- MSCC_PHY_REG_PHY_CFG + offset, 0x1ff);
+ ret = regmap_write(miim->phy_regs, offset, reset_bits);
if (ret < 0) {
WARN_ONCE(1, "mscc reset clear error %d\n", ret);
return ret;
miim = bus->priv;
miim->phy_regs = phy_regmap;
- miim->phy_reset_offset = 0;
+ miim->phy_reset_offset = MSCC_PHY_REG_PHY_CFG;
ret = of_mdiobus_register(bus, pdev->dev.of_node);
if (ret < 0) {