revert(cpus): "Revert workaround for A77 erratum 1800714"

Reinstate the workaround introduced in commit
9bbc03a6e0608a949d66d9da6db12a455b452bfb. The cited change to the SDEN
could not be found and there are no known problems with the workaround.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iec9938f173e7565024aca798f224df339de90806

diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 3477a042f7cf41c09933e6c31f2fe55abd83cf99..f736e2df0686815236025cb61d200d4fbadfb8d0 100644 (file)
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -273,6 +273,9 @@ For Cortex-A77, the following errata build flags are defined :
 -  ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77
    CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
 
+ -  ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77
+    CPU. This needs to be enabled for revisions <= r1p1 of the CPU.
+
 For Cortex-A78, the following errata build flags are defined :
 
 -  ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78

diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h
index 63f155f7b39370c85ad8ec2fdae87483d4973123..a9b45463d8212e18c939aca6861c736270b7dda8 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a77.h
+++ b/include/lib/cpus/aarch64/cortex_a77.h
@@ -20,6 +20,7 @@
  ******************************************************************************/
 #define CORTEX_A77_CPUECTLR_EL1                                S3_0_C15_C1_4
 #define CORTEX_A77_CPUECTLR_EL1_BIT_8                  (ULL(1) << 8)
+#define CORTEX_A77_CPUECTLR_EL1_BIT_53                 (ULL(1) << 53)
 
 /*******************************************************************************
  * CPU Power Control register specific definitions.

diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index aa66e94ea5b663d642e4dff474219bf679cd7c69..8cafe4a06912ae22cfcb15962e7b5e52bb081ab8 100644 (file)
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -236,6 +236,35 @@ func check_errata_cve_2022_23960
        ret
 endfunc check_errata_cve_2022_23960
 
+       /* --------------------------------------------------
+        * Errata Workaround for Cortex A77 Errata #1800714.
+        * This applies to revision <= r1p1 of Cortex A77.
+        * Inputs:
+        * x0: variant[4:7] and revision[0:3] of current cpu.
+        * Shall clobber: x0-x17
+        * --------------------------------------------------
+        */
+func errata_a77_1800714_wa
+       /* Compare x0 against revision <= r1p1 */
+       mov     x17, x30
+       bl      check_errata_1800714
+       cbz     x0, 1f
+
+       /* Disable allocation of splintered pages in the L2 TLB */
+       mrs     x1, CORTEX_A77_CPUECTLR_EL1
+       orr     x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53
+       msr     CORTEX_A77_CPUECTLR_EL1, x1
+       isb
+1:
+       ret     x17
+endfunc errata_a77_1800714_wa
+
+func check_errata_1800714
+       /* Applies to everything <= r1p1 */
+       mov     x1, #0x11
+       b       cpu_rev_var_ls
+endfunc check_errata_1800714
+
        /* -------------------------------------------------
         * The CPU Ops reset function for Cortex-A77.
         * Shall clobber: x0-x19
@@ -280,6 +309,11 @@ func cortex_a77_reset_func
        msr     vbar_el3, x0
 #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
 
+#if ERRATA_A77_1800714
+       mov     x0, x18
+       bl      errata_a77_1800714_wa
+#endif
+
        isb
        ret     x19
 endfunc cortex_a77_reset_func
@@ -315,9 +349,10 @@ func cortex_a77_errata_report
         * checking functions of each errata.
         */
        report_errata ERRATA_A77_1508412, cortex_a77, 1508412
+       report_errata ERRATA_A77_1791578, cortex_a77, 1791578
+       report_errata ERRATA_A77_1800714, cortex_a77, 1800714
        report_errata ERRATA_A77_1925769, cortex_a77, 1925769
        report_errata ERRATA_A77_1946167, cortex_a77, 1946167
-       report_errata ERRATA_A77_1791578, cortex_a77, 1791578
        report_errata ERRATA_A77_2356587, cortex_a77, 2356587
        report_errata WORKAROUND_CVE_2022_23960, cortex_a77, cve_2022_23960
 

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 08871f8a93815d53cd4273852276c57659db2044..8b790bcc12b584fb65b16092235096d4104bbe80 100644 (file)
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -307,6 +307,10 @@ ERRATA_A77_1791578 ?=0
 # to revisions r0p0, r1p0, and r1p1, it is still open.
 ERRATA_A77_2356587     ?=0
 
+# Flag to apply erratum 1800714 workaround during reset. This erratum applies
+# to revisions <= r1p1 of the Cortex A77 cpu.
+ERRATA_A77_1800714     ?=0
+
 # Flag to apply erratum 1688305 workaround during reset. This erratum applies
 # to revisions r0p0 - r1p0 of the A78 cpu.
 ERRATA_A78_1688305     ?=0
@@ -912,6 +916,10 @@ $(eval $(call add_define,ERRATA_A77_1791578))
 $(eval $(call assert_boolean,ERRATA_A77_2356587))
 $(eval $(call add_define,ERRATA_A77_2356587))
 
+# Process ERRATA_A77_1800714 flag
+$(eval $(call assert_boolean,ERRATA_A77_1800714))
+$(eval $(call add_define,ERRATA_A77_1800714))
+
 # Process ERRATA_A78_1688305 flag
 $(eval $(call assert_boolean,ERRATA_A78_1688305))
 $(eval $(call add_define,ERRATA_A78_1688305))