clk: qcom: cpu-8996: move ACD logic to clk_cpu_8996_pmux_determine_rate

Rather than telling everybody that we are using PLL as a parent (and
using ACD clock instead) properly select ACD as a pmux parent clock.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220714100351.1834711-5-dmitry.baryshkov@linaro.org

diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index 3dd6efdef82db5942c89ee6f7136b88fb3ea0c03..5c5adcb533ce8c188ea66f3a2573c82c712abb95 100644 (file)
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -284,9 +284,6 @@ static int clk_cpu_8996_pmux_set_parent(struct clk_hw *hw, u8 index)
        u32 val;
 
        val = index;
-       /* We always want ACD when using the primary PLL */
-       if (val == PLL_INDEX)
-               val = ACD_INDEX;
        val <<= cpuclk->shift;
 
        return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val);
@@ -371,7 +368,7 @@ static struct clk_cpu_8996_pmux pwrcl_pmux = {
        .reg = PWRCL_REG_OFFSET + MUX_OFFSET,
        .shift = 0,
        .width = 2,
-       .pll = &pwrcl_pll.clkr.hw,
+       .pll = &pwrcl_pll_acd.clkr.hw,
        .pll_div_2 = &pwrcl_smux.clkr.hw,
        .nb.notifier_call = cpu_clk_notifier_cb,
        .clkr.hw.init = &(struct clk_init_data) {
@@ -388,7 +385,7 @@ static struct clk_cpu_8996_pmux perfcl_pmux = {
        .reg = PERFCL_REG_OFFSET + MUX_OFFSET,
        .shift = 0,
        .width = 2,
-       .pll = &perfcl_pll.clkr.hw,
+       .pll = &perfcl_pll_acd.clkr.hw,
        .pll_div_2 = &perfcl_smux.clkr.hw,
        .nb.notifier_call = cpu_clk_notifier_cb,
        .clkr.hw.init = &(struct clk_init_data) {