drm/i915: Extract i915_cs_timestamp_{ns_to_ticks,tick_to_ns}()

Pull the code to do the CS timestamp ns<->ticks conversion into
helpers and use them all over.

The check in i915_perf_noa_delay_set() seems a bit dubious,
so we switch it to do what I assume it wanted to do all along
(ie. make sure the resulting delay in CS timestamp ticks
doesn't exceed 32bits)?

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200302143943.32676-5-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 1469ea1e85f2fda05f64cb723e61ef1197c287b7..4481feb34bc57066f9ca70c7bb666e73c20b4089 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1404,13 +1404,12 @@ static int
 i915_perf_noa_delay_set(void *data, u64 val)
 {
        struct drm_i915_private *i915 = data;
-       const u32 clk = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz / 1000;
 
        /*
         * This would lead to infinite waits as we're doing timestamp
         * difference on the CS with only 32bits.
         */
-       if (val > mul_u32_u32(U32_MAX, clk))
+       if (i915_cs_timestamp_ns_to_ticks(i915, val) > U32_MAX)
                return -EINVAL;
 
        atomic64_set(&i915->perf.noa_programming_delay, val);

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ad373b57699a068d0e7b7748b61bb8f1115b9bb7..13937175ab669967c0771e0c86c06e7d2a963469 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1921,4 +1921,16 @@ i915_coherent_map_type(struct drm_i915_private *i915)
        return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
 }
 
+static inline u64 i915_cs_timestamp_ns_to_ticks(struct drm_i915_private *i915, u64 val)
+{
+       return DIV_ROUND_UP_ULL(val * RUNTIME_INFO(i915)->cs_timestamp_frequency_hz,
+                               1000000000);
+}
+
+static inline u64 i915_cs_timestamp_ticks_to_ns(struct drm_i915_private *i915, u64 val)
+{
+       return div_u64(val * 1000000000,
+                      RUNTIME_INFO(i915)->cs_timestamp_frequency_hz);
+}
+
 #endif

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 205327c6c34233fc7d36efb49f7b62f7fb58867d..f35712d04ba499667e5a4f0ae7a3e4b00cd78683 100644 (file)
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1612,9 +1612,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
        struct drm_i915_gem_object *bo;
        struct i915_vma *vma;
        const u64 delay_ticks = 0xffffffffffffffff -
-               DIV_ROUND_UP_ULL(atomic64_read(&stream->perf->noa_programming_delay) *
-                                RUNTIME_INFO(i915)->cs_timestamp_frequency_hz,
-                                1000000000);
+               i915_cs_timestamp_ns_to_ticks(i915, atomic64_read(&stream->perf->noa_programming_delay));
        const u32 base = stream->engine->mmio_base;
 #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
        u32 *batch, *ts0, *cs, *jump;
@@ -3484,8 +3482,7 @@ err:
 
 static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
 {
-       return div_u64(1000000000 * (2ULL << exponent),
-                      RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_hz);
+       return i915_cs_timestamp_ticks_to_ns(perf->i915, 2ULL << exponent);
 }
 
 /**

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 7277d86f0d3f9d5e597fcc2637e39007a4168282..8a635bd4d5d8a01c0795591f1d28309cdde230c3 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -1052,7 +1052,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
                read_timestamp_frequency(dev_priv);
        if (runtime->cs_timestamp_frequency_hz) {
                runtime->cs_timestamp_period_ns =
-                       div_u64(1e9, runtime->cs_timestamp_frequency_hz);
+                       i915_cs_timestamp_ticks_to_ns(dev_priv, 1);
                drm_dbg(&dev_priv->drm,
                        "CS timestamp wraparound in %lldms\n",
                        div_u64(mul_u32_u32(runtime->cs_timestamp_period_ns,

diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c
index 5edfcfd42a31e71b3378bd005f7ac99fc7a1662c..8eb3108f1767a7f42e5ed101868ab096055104f1 100644 (file)
--- a/drivers/gpu/drm/i915/selftests/i915_perf.c
+++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
@@ -262,8 +262,7 @@ static int live_noa_delay(void *arg)
 
        delay = intel_read_status_page(stream->engine, 0x102);
        delay -= intel_read_status_page(stream->engine, 0x100);
-       delay = div_u64(mul_u32_u32(delay, 1000000000),
-                       RUNTIME_INFO(i915)->cs_timestamp_frequency_hz);
+       delay = i915_cs_timestamp_ticks_to_ns(i915, delay);
        pr_info("GPU delay: %uns, expected %lluns\n",
                delay, expected);