return 0;
}
-static int intel_ddi_dp_level(struct intel_dp *intel_dp)
+static int intel_ddi_dp_level(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
{
u8 train_set = intel_dp->train_set[0];
u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
const struct intel_crtc_state *crtc_state)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
- int level = intel_ddi_dp_level(intel_dp);
+ int level = intel_ddi_dp_level(intel_dp, crtc_state);
intel_snps_phy_ddi_vswing_sequence(encoder, level);
}
const struct intel_crtc_state *crtc_state)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
- int level = intel_ddi_dp_level(intel_dp);
+ int level = intel_ddi_dp_level(intel_dp, crtc_state);
tgl_ddi_vswing_sequence(encoder, crtc_state, level);
}
const struct intel_crtc_state *crtc_state)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
- int level = intel_ddi_dp_level(intel_dp);
+ int level = intel_ddi_dp_level(intel_dp, crtc_state);
icl_ddi_vswing_sequence(encoder, crtc_state, level);
}
const struct intel_crtc_state *crtc_state)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
- int level = intel_ddi_dp_level(intel_dp);
+ int level = intel_ddi_dp_level(intel_dp, crtc_state);
bxt_ddi_vswing_sequence(encoder, crtc_state, level);
}
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- int level = intel_ddi_dp_level(intel_dp);
+ int level = intel_ddi_dp_level(intel_dp, crtc_state);
enum port port = encoder->port;
u32 signal_levels;
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
- int level = intel_ddi_dp_level(intel_dp);
+ int level = intel_ddi_dp_level(intel_dp, crtc_state);
intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
crtc_state->lane_count);
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
- int level = intel_ddi_dp_level(intel_dp);
+ int level = intel_ddi_dp_level(intel_dp, crtc_state);
intel_dp_set_link_params(intel_dp,
crtc_state->port_clock,
enum phy phy = intel_port_to_phy(dev_priv, port);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
- int level = intel_ddi_dp_level(intel_dp);
+ int level = intel_ddi_dp_level(intel_dp, crtc_state);
if (DISPLAY_VER(dev_priv) < 11)
drm_WARN_ON(&dev_priv->drm,