]> git.baikalelectronics.ru Git - arm-tf.git/commitdiff
lib: el3_runtime: Conditionally save/restore EL2 NEVE registers
authorArunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Thu, 28 May 2020 10:57:09 +0000 (11:57 +0100)
committerManish Pandey <manish.pandey2@arm.com>
Tue, 20 Oct 2020 20:06:43 +0000 (20:06 +0000)
Include EL2 registers related to Nested Virtualization in EL2 context
save/restore routines if architecture supports it and platform wants to
use these features in Secure world.

Change-Id: If006ab83bbc2576488686f5ffdff88b91adced5c
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Makefile
docs/getting_started/build-options.rst
lib/el3_runtime/aarch64/context.S
make_helpers/defaults.mk

index c5073e016b512f4bc62620672392b65b7d083730..961423826a199a61023a6f54fe54ec628b97923d 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -865,6 +865,7 @@ $(eval $(call assert_booleans,\
         CTX_INCLUDE_PAUTH_REGS \
         CTX_INCLUDE_MTE_REGS \
         CTX_INCLUDE_EL2_REGS \
+        CTX_INCLUDE_NEVE_REGS \
         DEBUG \
         DYN_DISABLE_AUTH \
         EL3_EXCEPTION_HANDLING \
@@ -953,6 +954,7 @@ $(eval $(call add_defines,\
         EL3_EXCEPTION_HANDLING \
         CTX_INCLUDE_MTE_REGS \
         CTX_INCLUDE_EL2_REGS \
+        CTX_INCLUDE_NEVE_REGS \
         DECRYPTION_SUPPORT_${DECRYPTION_SUPPORT} \
         ENABLE_AMU \
         ENABLE_ASSERTIONS \
index 40fc5dbbc909bec06ce34eb6551b763684969a85..8adf4ad8ba2a3e351486471ba7faf776fa0a28a2 100644 (file)
@@ -161,6 +161,10 @@ Common build options
    registers to be included when saving and restoring the CPU context. Default
    is 0.
 
+-  ``CTX_INCLUDE_NEVE_REGS``: Boolean option that, when set to 1, will cause the
+   Armv8.4-NV registers to be saved/restored when entering/exiting an EL2
+   execution context. Default value is 0.
+
 -  ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
    Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
    registers to be included when saving and restoring the CPU context as
index 785e850934e7d64eb9e0cd8b5bde31fdb1bd1fbb..c942c10ecec0005d80ad138d10aaba90e5e29e71 100644 (file)
@@ -200,8 +200,10 @@ func el2_sysregs_context_save
        mrs     x12, vdisr_el2
        str     x12, [x0, #CTX_VDISR_EL2]
 
+#if CTX_INCLUDE_NEVE_REGS
        mrs     x13, vncr_el2
        str     x13, [x0, #CTX_VNCR_EL2]
+#endif
 
        mrs     x14, vsesr_el2
        str     x14, [x0, #CTX_VSESR_EL2]
@@ -395,8 +397,10 @@ func el2_sysregs_context_restore
        ldr     x13, [x0, #CTX_VDISR_EL2]
        msr     vdisr_el2, x13
 
+#if CTX_INCLUDE_NEVE_REGS
        ldr     x14, [x0, #CTX_VNCR_EL2]
        msr     vncr_el2, x14
+#endif
 
        ldr     x15, [x0, #CTX_VSESR_EL2]
        msr     vsesr_el2, x15
index bc4982d64dcc40c148b71a135999590034c9337b..578bd59876a8681ab7e2ae8b78eba0aa063ea5e1 100644 (file)
@@ -62,6 +62,11 @@ CTX_INCLUDE_FPREGS           := 0
 # world. It is not needed to use it in the Non-secure world.
 CTX_INCLUDE_PAUTH_REGS         := 0
 
+# Include Nested virtualization control (Armv8.4-NV) registers in cpu context.
+# This must be set to 1 if architecture implements Nested Virtualization
+# Extension and platform wants to use this feature in the Secure world
+CTX_INCLUDE_NEVE_REGS          := 0
+
 # Debug build
 DEBUG                          := 0