]> git.baikalelectronics.ru Git - kernel.git/commitdiff
arm64: cpufeature: add HWCAP for FEAT_RPRES
authorJoey Gouly <joey.gouly@arm.com>
Fri, 10 Dec 2021 16:54:32 +0000 (16:54 +0000)
committerCatalin Marinas <catalin.marinas@arm.com>
Mon, 13 Dec 2021 18:53:00 +0000 (18:53 +0000)
Add a new HWCAP to detect the Increased precision of Reciprocal Estimate
and Reciprocal Square Root Estimate feature (FEAT_RPRES), introduced in Armv8.7.

Also expose this to userspace in the ID_AA64ISAR2_EL1 feature register.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211210165432.8106-4-joey.gouly@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Documentation/arm64/cpu-feature-registers.rst
Documentation/arm64/elf_hwcaps.rst
arch/arm64/include/asm/hwcap.h
arch/arm64/include/uapi/asm/hwcap.h
arch/arm64/kernel/cpufeature.c
arch/arm64/kernel/cpuinfo.c

index 1b19d20c2dbd62632f2a18504e4e03a4f6dcf047..749ae970c31955a6ddd54807d4f7a0700cf85295 100644 (file)
@@ -283,6 +283,14 @@ infrastructure:
      | AFP                          | [47-44] |    y    |
      +------------------------------+---------+---------+
 
+  9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2
+
+     +------------------------------+---------+---------+
+     | Name                         |  bits   | visible |
+     +------------------------------+---------+---------+
+     | RPRES                        | [7-4]   |    y    |
+     +------------------------------+---------+---------+
+
 
 Appendix I: Example
 -------------------
index 247728d3791182eacb02d873d20cba209ce6e736..b72ff17d600aee7932157e993e580f41a2a7c426 100644 (file)
@@ -255,6 +255,10 @@ HWCAP2_AFP
 
     Functionality implied by ID_AA64MFR1_EL1.AFP == 0b0001.
 
+HWCAP2_RPRES
+
+    Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001.
+
 4. Unused AT_HWCAP bits
 -----------------------
 
index 2809df2fdd63a7aa4e2688dff74102a6a68179bc..f68fbb207473047d7756cb2cc1b2bc29e4c4da03 100644 (file)
 #define KERNEL_HWCAP_MTE               __khwcap2_feature(MTE)
 #define KERNEL_HWCAP_ECV               __khwcap2_feature(ECV)
 #define KERNEL_HWCAP_AFP               __khwcap2_feature(AFP)
+#define KERNEL_HWCAP_RPRES             __khwcap2_feature(RPRES)
 
 /*
  * This yields a mask that user programs can use to figure out what
index 180da7396549c6640e7d41df37c4b09dc1ac8dac..f03731847d9dfdbed849baceafb61f91745bd1cc 100644 (file)
@@ -77,5 +77,6 @@
 #define HWCAP2_MTE             (1 << 18)
 #define HWCAP2_ECV             (1 << 19)
 #define HWCAP2_AFP             (1 << 20)
+#define HWCAP2_RPRES           (1 << 21)
 
 #endif /* _UAPI__ASM_HWCAP_H */
index c36018310da5b66b009800748dad17603e7a9326..a46ab3b1c4d5f9e949dc3692bdebb5e470161fd0 100644 (file)
@@ -226,6 +226,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 };
 
 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
@@ -2487,6 +2488,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
 #endif /* CONFIG_ARM64_MTE */
        HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
        HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
+       HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
        {},
 };
 
index f2f8fe02f39c71a7dbfc644fd8446cda18a51e08..591c18a889a56fee002fecce7f686c598bb92244 100644 (file)
@@ -96,6 +96,7 @@ static const char *const hwcap_str[] = {
        [KERNEL_HWCAP_MTE]              = "mte",
        [KERNEL_HWCAP_ECV]              = "ecv",
        [KERNEL_HWCAP_AFP]              = "afp",
+       [KERNEL_HWCAP_RPRES]            = "rpres",
 };
 
 #ifdef CONFIG_COMPAT