drm/i915: Use enum pipe instead of crtc index to track active pipes

We may need to eliminate the crtc->index == pipe assumptions from
the code to support arbitrary pipes being fused off. Start that by
switching some bitmasks over to using pipe instead of the crtc index.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190821173033.24123-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d0bc42e5039c4e517127f209cbcaec6adcef4009..939088c7d81437a70b98bd0178566fa89060c6ce 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2369,7 +2369,7 @@ static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
        state->cdclk.logical.voltage_level =
                vlv_calc_voltage_level(dev_priv, cdclk);
 
-       if (!state->active_crtcs) {
+       if (!state->active_pipes) {
                cdclk = vlv_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
 
                state->cdclk.actual.cdclk = cdclk;
@@ -2400,7 +2400,7 @@ static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
        state->cdclk.logical.voltage_level =
                bdw_calc_voltage_level(cdclk);
 
-       if (!state->active_crtcs) {
+       if (!state->active_pipes) {
                cdclk = bdw_calc_cdclk(state->cdclk.force_min_cdclk);
 
                state->cdclk.actual.cdclk = cdclk;
@@ -2470,7 +2470,7 @@ static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
        state->cdclk.logical.voltage_level =
                skl_calc_voltage_level(cdclk);
 
-       if (!state->active_crtcs) {
+       if (!state->active_pipes) {
                cdclk = skl_calc_cdclk(state->cdclk.force_min_cdclk, vco);
 
                state->cdclk.actual.vco = vco;
@@ -2506,7 +2506,7 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
        state->cdclk.logical.voltage_level =
                bxt_calc_voltage_level(cdclk);
 
-       if (!state->active_crtcs) {
+       if (!state->active_pipes) {
                if (IS_GEMINILAKE(dev_priv)) {
                        cdclk = glk_calc_cdclk(state->cdclk.force_min_cdclk);
                        vco = glk_de_pll_vco(dev_priv, cdclk);
@@ -2544,7 +2544,7 @@ static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
                max(cnl_calc_voltage_level(cdclk),
                    cnl_compute_min_voltage_level(state));
 
-       if (!state->active_crtcs) {
+       if (!state->active_pipes) {
                cdclk = cnl_calc_cdclk(state->cdclk.force_min_cdclk);
                vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
 
@@ -2578,7 +2578,7 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
                max(icl_calc_voltage_level(dev_priv, cdclk),
                    cnl_compute_min_voltage_level(state));
 
-       if (!state->active_crtcs) {
+       if (!state->active_pipes) {
                cdclk = icl_calc_cdclk(state->cdclk.force_min_cdclk, ref);
                vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
 

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b51d1ceb873937761dc16bd2690e3fc3fe85c9db..7b74df03a1ef2bac41ee85130a82b36f084036ea 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7080,7 +7080,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
                intel_display_power_put_unchecked(dev_priv, domain);
        intel_crtc->enabled_power_domains = 0;
 
-       dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
+       dev_priv->active_pipes &= ~BIT(intel_crtc->pipe);
        dev_priv->min_cdclk[intel_crtc->pipe] = 0;
        dev_priv->min_voltage_level[intel_crtc->pipe] = 0;
 
@@ -13452,7 +13452,7 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
                state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
 
        state->modeset = true;
-       state->active_crtcs = dev_priv->active_crtcs;
+       state->active_pipes = dev_priv->active_pipes;
        state->cdclk.logical = dev_priv->cdclk.logical;
        state->cdclk.actual = dev_priv->cdclk.actual;
        state->cdclk.pipe = INVALID_PIPE;
@@ -13460,12 +13460,12 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
        for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
                                            new_crtc_state, i) {
                if (new_crtc_state->base.active)
-                       state->active_crtcs |= 1 << i;
+                       state->active_pipes |= BIT(crtc->pipe);
                else
-                       state->active_crtcs &= ~(1 << i);
+                       state->active_pipes &= ~BIT(crtc->pipe);
 
                if (old_crtc_state->base.active != new_crtc_state->base.active)
-                       state->active_pipe_changes |= drm_crtc_mask(&crtc->base);
+                       state->active_pipe_changes |= BIT(crtc->pipe);
        }
 
        /*
@@ -13494,11 +13494,11 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
                                return ret;
                }
 
-               if (is_power_of_2(state->active_crtcs)) {
+               if (is_power_of_2(state->active_pipes)) {
                        struct intel_crtc *crtc;
                        struct intel_crtc_state *crtc_state;
 
-                       pipe = ilog2(state->active_crtcs);
+                       pipe = ilog2(state->active_pipes);
                        crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
                        crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
                        if (crtc_state && needs_modeset(crtc_state))
@@ -14191,7 +14191,7 @@ static int intel_atomic_commit(struct drm_device *dev,
                       sizeof(state->min_cdclk));
                memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
                       sizeof(state->min_voltage_level));
-               dev_priv->active_crtcs = state->active_crtcs;
+               dev_priv->active_pipes = state->active_pipes;
                dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
 
                intel_cdclk_swap_state(state);
@@ -16640,7 +16640,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
        struct drm_connector_list_iter conn_iter;
        int i;
 
-       dev_priv->active_crtcs = 0;
+       dev_priv->active_pipes = 0;
 
        for_each_intel_crtc(dev, crtc) {
                struct intel_crtc_state *crtc_state =
@@ -16657,7 +16657,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
                crtc->active = crtc_state->base.active;
 
                if (crtc_state->base.active)
-                       dev_priv->active_crtcs |= 1 << crtc->pipe;
+                       dev_priv->active_pipes |= BIT(crtc->pipe);
 
                DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
                              crtc->base.base.id, crtc->base.name,

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 449abaea619fccde2e997a968d6d5e069344a0db..12523456143f404a766fb9972b67617d48ccc3eb 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -481,9 +481,9 @@ struct intel_atomic_state {
         * but the converse is not necessarily true; simply changing a mode may
         * not flip the final active status of any CRTC's
         */
-       unsigned int active_pipe_changes;
+       u8 active_pipe_changes;
 
-       unsigned int active_crtcs;
+       u8 active_pipes;
        /* minimum acceptable cdclk for each pipe */
        int min_cdclk[I915_MAX_PIPES];
        /* minimum acceptable voltage level for each pipe */

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 048896b1348b9eb5aaebc05a7a3e05b941b9175b..ba3f6d82ef26af0a71d27d662263c231b4ce6705 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1468,7 +1468,7 @@ struct drm_i915_private {
         */
        struct mutex dpll_lock;
 
-       unsigned int active_crtcs;
+       u8 active_pipes;
        /* minimum acceptable cdclk for each pipe */
        int min_cdclk[I915_MAX_PIPES];
        /* minimum acceptable voltage level for each pipe */

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d3ea193cd093907a3d14fb60c7d11c2c5ed5f70b..09f29a337313ff8fb5751858ee61a984bdd3f669 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3761,18 +3761,18 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
        /*
         * If there are no active CRTCs, no additional checks need be performed
         */
-       if (hweight32(state->active_crtcs) == 0)
+       if (hweight32(state->active_pipes) == 0)
                return true;
 
        /*
         * SKL+ workaround: bspec recommends we disable SAGV when we have
         * more then one pipe enabled
         */
-       if (hweight32(state->active_crtcs) > 1)
+       if (hweight32(state->active_pipes) > 1)
                return false;
 
        /* Since we're now guaranteed to only have one active CRTC... */
-       pipe = ffs(state->active_crtcs) - 1;
+       pipe = ffs(state->active_pipes) - 1;
        crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
        crtc_state = to_intel_crtc_state(crtc->base.state);
 
@@ -3867,14 +3867,14 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
        if (WARN_ON(!state) || !crtc_state->base.active) {
                alloc->start = 0;
                alloc->end = 0;
-               *num_active = hweight32(dev_priv->active_crtcs);
+               *num_active = hweight32(dev_priv->active_pipes);
                return;
        }
 
        if (intel_state->active_pipe_changes)
-               *num_active = hweight32(intel_state->active_crtcs);
+               *num_active = hweight32(intel_state->active_pipes);
        else
-               *num_active = hweight32(dev_priv->active_crtcs);
+               *num_active = hweight32(dev_priv->active_pipes);
 
        ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate,
                                      *num_active, ddb);
@@ -5464,7 +5464,7 @@ skl_ddb_add_affected_pipes(struct intel_atomic_state *state, bool *changed)
         * If this transaction isn't actually touching any CRTC's, don't
         * bother with watermark calculation.  Note that if we pass this
         * test, we're guaranteed to hold at least one CRTC state mutex,
-        * which means we can safely use values like dev_priv->active_crtcs
+        * which means we can safely use values like dev_priv->active_pipes
         * since any racing commits that want to update them would need to
         * hold _all_ CRTC state mutexes.
         */
@@ -5489,13 +5489,13 @@ skl_ddb_add_affected_pipes(struct intel_atomic_state *state, bool *changed)
                state->active_pipe_changes = ~0;
 
                /*
-                * We usually only initialize state->active_crtcs if we
+                * We usually only initialize state->active_pipes if we
                 * we're doing a modeset; make sure this field is always
                 * initialized during the sanitization process that happens
                 * on the first commit too.
                 */
                if (!state->modeset)
-                       state->active_crtcs = dev_priv->active_crtcs;
+                       state->active_pipes = dev_priv->active_pipes;
        }
 
        /*
@@ -5811,7 +5811,7 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
                        hw->dirty_pipes |= drm_crtc_mask(&crtc->base);
        }
 
-       if (dev_priv->active_crtcs) {
+       if (dev_priv->active_pipes) {
                /* Fully recompute DDB on first atomic commit */
                dev_priv->wm.distrust_bios_wm = true;
        }