arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy

Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.

Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index 9ad7594e76225f4c75b2dc4cbce33cd822457bce..e966e3a3c93190e5704d4fdcfe6cce3a17db10f9 100644 (file)
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -357,6 +357,10 @@
 #define DRA7XX_CM_L3INIT_SATA_CLKCTRL                          DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
 #define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET                                0x00a0
 #define DRA7XX_CM_PCIE_STATICDEP_OFFSET                                0x00a4
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET                        0x00b0
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL                       DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET                        0x00b8
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL                       DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
 #define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET                                0x00c0
 #define DRA7XX_CM_GMAC_STATICDEP_OFFSET                                0x00c4
 #define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET                       0x00c8

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index c9daee46d9802b962fef0ddc46fd8cde043df131..b21647d7532ccb2d14eb668f48c446aa27331192 100644 (file)
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1230,6 +1230,45 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
        },
 };
 
+/*
+ * 'PCIE PHY' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
+       .name   = "pcie-phy",
+};
+
+/* pcie1 phy */
+static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
+       .name           = "pcie1-phy",
+       .class          = &dra7xx_pcie_phy_hwmod_class,
+       .clkdm_name     = "l3init_clkdm",
+       .main_clk       = "l4_root_clk_div",
+       .prcm = {
+               .omap4 = {
+                       .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
+                       .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
+                       .modulemode   = MODULEMODE_SWCTRL,
+               },
+       },
+};
+
+/* pcie2 phy */
+static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
+       .name           = "pcie2-phy",
+       .class          = &dra7xx_pcie_phy_hwmod_class,
+       .clkdm_name     = "l3init_clkdm",
+       .main_clk       = "l4_root_clk_div",
+       .prcm = {
+               .omap4 = {
+                       .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
+                       .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
+                       .modulemode   = MODULEMODE_SWCTRL,
+               },
+       },
+};
+
 /*
  * 'qspi' class
  *
@@ -2349,6 +2388,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_cfg -> pcie1 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
+       .master         = &dra7xx_l4_cfg_hwmod,
+       .slave          = &dra7xx_pcie1_phy_hwmod,
+       .clk            = "l4_root_clk_div",
+       .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
+       .master         = &dra7xx_l4_cfg_hwmod,
+       .slave          = &dra7xx_pcie2_phy_hwmod,
+       .clk            = "l4_root_clk_div",
+       .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
        {
                .pa_start       = 0x4b300000,
@@ -2696,6 +2751,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
        &dra7xx_l4_cfg__mpu,
        &dra7xx_l4_cfg__ocp2scp1,
        &dra7xx_l4_cfg__ocp2scp3,
+       &dra7xx_l4_cfg__pcie1_phy,
+       &dra7xx_l4_cfg__pcie2_phy,
        &dra7xx_l3_main_1__qspi,
        &dra7xx_l4_cfg__sata,
        &dra7xx_l4_cfg__smartreflex_core,

diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index d92a8404edc778c7c01bf82c561c5e724b8b7741..4bb50fbf29bebb5f546edf866665dcd29bb11d36 100644 (file)
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -374,6 +374,10 @@
 #define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET         0x007c
 #define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET                     0x0088
 #define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET                   0x008c
+#define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET                  0x00b0
+#define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET                0x00b4
+#define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET                  0x00b8
+#define DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET                0x00bc
 #define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET                     0x00d4
 #define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET               0x00e4
 #define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET               0x00ec