expected = 0;
for_each_pci_msi_entry(entry, pdev) {
- if (entry->pci.msi_attrib.entry_nr != expected) {
+ if (entry->msi_index != expected) {
pr_debug("rtas_msi: bad MSI-X entries.\n");
return -EINVAL;
}
int hwirq;
int i, ret;
- hwirq = rtas_query_irq_number(pci_get_pdn(pdev), desc->pci.msi_attrib.entry_nr);
+ hwirq = rtas_query_irq_number(pci_get_pdn(pdev), desc->msi_index);
if (hwirq < 0) {
dev_err(&pdev->dev, "Failed to query HW IRQ: %d\n", hwirq);
return hwirq;
static inline void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
{
- return desc->pci.mask_base + desc->pci.msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
+ return desc->pci.mask_base + desc->msi_index * PCI_MSIX_ENTRY_SIZE;
}
/*
if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING)
control |= PCI_MSI_FLAGS_MASKBIT;
- entry->pci.msi_attrib.is_msix = 0;
- entry->pci.msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
- entry->pci.msi_attrib.is_virtual = 0;
- entry->pci.msi_attrib.entry_nr = 0;
+ entry->pci.msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
entry->pci.msi_attrib.can_mask = !pci_msi_ignore_mask &&
!!(control & PCI_MSI_FLAGS_MASKBIT);
- entry->pci.msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
+ entry->pci.msi_attrib.default_irq = dev->irq;
entry->pci.msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
entry->pci.msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
entry->pci.msi_attrib.is_64 = 1;
if (entries)
- entry->pci.msi_attrib.entry_nr = entries[i].entry;
+ entry->msi_index = entries[i].entry;
else
- entry->pci.msi_attrib.entry_nr = i;
+ entry->msi_index = i;
- entry->pci.msi_attrib.is_virtual =
- entry->pci.msi_attrib.entry_nr >= vec_count;
+ entry->pci.msi_attrib.is_virtual = entry->msi_index >= vec_count;
entry->pci.msi_attrib.can_mask = !pci_msi_ignore_mask &&
!entry->pci.msi_attrib.is_virtual;
struct msi_desc *entry;
for_each_pci_msi_entry(entry, dev) {
- if (entry->pci.msi_attrib.entry_nr == nr)
+ if (entry->msi_index == nr)
return entry->irq;
}
WARN_ON_ONCE(1);
struct msi_desc *entry;
for_each_pci_msi_entry(entry, dev) {
- if (entry->pci.msi_attrib.entry_nr == nr)
+ if (entry->msi_index == nr)
return &entry->affinity->mask;
}
WARN_ON_ONCE(1);
* @multi_cap: [PCI MSI/X] log2 num of messages supported
* @can_mask: [PCI MSI/X] Masking supported?
* @is_64: [PCI MSI/X] Address size: 0=32bit 1=64bit
- * @entry_nr: [PCI MSI/X] Entry which is described by this descriptor
* @default_irq:[PCI MSI/X] The default pre-assigned non-MSI irq
* @mask_pos: [PCI MSI] Mask register position
* @mask_base: [PCI MSI-X] Mask register base address
u8 can_mask : 1;
u8 is_64 : 1;
u8 is_virtual : 1;
- u16 entry_nr;
unsigned default_irq;
} msi_attrib;
union {