config ENABLE_36BIT_PHYS
bool "Enable 36bit physical address space support"
+config SYS_BOOK3E_HV
+ bool "Category E.HV is supported"
+ depends on BOOKE
+
config SYS_MPC85XX_NO_RESETVEC
bool "Discard resetvec section and move bootpg section up"
depends on MPC85xx
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_TARGET_P4080DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_TARGET_P4080DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_TARGET_P4080DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_TARGET_T1024RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_NXP_ESBC=y
CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000
CONFIG_PCIE1=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SRIO_PCIE_BOOT_SLAVE=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======
CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
-<<<<<<< HEAD
-=======
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
->>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
<<<<<<< HEAD
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
<<<<<<< HEAD
CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_T2080RDB_REV_D=y
<<<<<<< HEAD
=======
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======
CONFIG_TARGET_T4240RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
-<<<<<<< HEAD
-=======
+CONFIG_SYS_BOOK3E_HV=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
->>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_TARGET_KMCENT2=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
+CONFIG_SYS_BOOK3E_HV=y
# CONFIG_DEEP_SLEEP is not set
CONFIG_PCIE1=y
CONFIG_KM_DEF_NETDEV="eth2"
#endif
/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#include <linux/stringify.h>
/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#endif
/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#endif /* CONFIG_RAMBOOT_PBL */
/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#define KM_I2C_DEBLOCK_SDA 21
/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc