drm/amd/display: implement notify stream mask

[Why]
Send stream active state info to DMUB

[How]
Implement GPINT to notify stream mask

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index ce5303c76b118c1b76f9c4547c21c98bcef8012c..1190c58275c3aad35b3ec4f9109fcb50a7cbd472 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1246,6 +1246,19 @@ void dc_trigger_sync(struct dc *dc, struct dc_state *context)
        }
 }
 
+static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
+{
+       int i;
+       unsigned int stream_mask = 0;
+
+       for (i = 0; i < dc->res_pool->pipe_count; i++) {
+               if (context->res_ctx.pipe_ctx[i].stream)
+                       stream_mask |= 1 << i;
+       }
+
+       return stream_mask;
+}
+
 /*
  * Applies given context to HW and copy it into current context.
  * It's up to the user to release the src context afterwards.
@@ -1362,6 +1375,11 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
                dc->hwss.optimize_bandwidth(dc, context);
        }
 
+       context->stream_mask = get_stream_mask(dc, context);
+
+       if (context->stream_mask != dc->current_state->stream_mask)
+               dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
+
        for (i = 0; i < context->stream_count; i++)
                context->streams[i]->mode_changed = false;
 

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index eea2429ac67d8a93273e65d1820456795d692ca4..b987548119772544db73e9c0d7ac0c4278d0327d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -132,3 +132,19 @@ void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv)
                /* Continue spinning so we don't hang the ASIC. */
        }
 }
+
+bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
+                                   unsigned int stream_mask)
+{
+       struct dmub_srv *dmub;
+       const uint32_t timeout = 30;
+
+       if (!dc_dmub_srv || !dc_dmub_srv->dmub)
+               return false;
+
+       dmub = dc_dmub_srv->dmub;
+
+       return dmub_srv_send_gpint_command(
+                      dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,
+                      stream_mask, timeout) == DMUB_STATUS_OK;
+}

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
index a3a09ccb6d266c20514eb30b8a03834e840737ca..bb4ab61887e4cc8d9373ea37ccd2b236540e9f8a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
@@ -56,4 +56,6 @@ void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv);
 
 void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv);
 
+bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
+                                   unsigned int stream_mask);
 #endif /* _DMUB_DC_SRV_H_ */

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 3ec1d9dd1670071895b97821a03d5f4629fb4cf9..1daa563c8ff44bbca68cb0afeae8d928fb0d98a1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -397,6 +397,7 @@ struct dc_state {
        struct dc_stream_state *streams[MAX_PIPES];
        struct dc_stream_status stream_status[MAX_PIPES];
        uint8_t stream_count;
+       uint8_t stream_mask;
 
        struct resource_context res_ctx;