]> git.baikalelectronics.ru Git - kernel.git/commitdiff
clk: at91: fix the build with binutils 2.27
authorKefeng Wang <wangkefeng.wang@huawei.com>
Wed, 12 Oct 2022 03:06:35 +0000 (11:06 +0800)
committerStephen Boyd <sboyd@kernel.org>
Fri, 14 Oct 2022 20:39:23 +0000 (13:39 -0700)
There is an issue when build with older versions of binutils 2.27.0,

arch/arm/mach-at91/pm_suspend.S: Assembler messages:
arch/arm/mach-at91/pm_suspend.S:1086: Error: garbage following instruction -- `ldr tmp1,=0x00020010UL'

Use UL() macro to fix the issue in assembly file.

Fixes: 5a86df757815 ("ARM: at91: pm: add plla disable/enable support for sam9x60")
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Link: https://lore.kernel.org/r/20221012030635.13140-1-wangkefeng.wang@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
include/linux/clk/at91_pmc.h

index 3484309b59bf1855244b97d7b89863fe4539d273..7af499bdbecb9dedd8309821ffb541ad33bf1d50 100644 (file)
@@ -12,6 +12,8 @@
 #ifndef AT91_PMC_H
 #define AT91_PMC_H
 
+#include <linux/bits.h>
+
 #define AT91_PMC_V1            (1)                     /* PMC version 1 */
 #define AT91_PMC_V2            (2)                     /* PMC version 2 [SAM9X60] */
 
@@ -45,8 +47,8 @@
 #define        AT91_PMC_PCSR           0x18                    /* Peripheral Clock Status Register */
 
 #define AT91_PMC_PLL_ACR       0x18                    /* PLL Analog Control Register [for SAM9X60] */
-#define                AT91_PMC_PLL_ACR_DEFAULT_UPLL   0x12020010UL    /* Default PLL ACR value for UPLL */
-#define                AT91_PMC_PLL_ACR_DEFAULT_PLLA   0x00020010UL    /* Default PLL ACR value for PLLA */
+#define                AT91_PMC_PLL_ACR_DEFAULT_UPLL   UL(0x12020010)  /* Default PLL ACR value for UPLL */
+#define                AT91_PMC_PLL_ACR_DEFAULT_PLLA   UL(0x00020010)  /* Default PLL ACR value for PLLA */
 #define                AT91_PMC_PLL_ACR_UTMIVR         (1 << 12)       /* UPLL Voltage regulator Control */
 #define                AT91_PMC_PLL_ACR_UTMIBG         (1 << 13)       /* UPLL Bandgap Control */