drm/i915/xehp: Support platforms with CCS engines but no RCS

In the past we've always assumed that an RCS engine is present on every
platform.  However now that we have compute engines there may be
platforms that have CCS engines but no RCS, or platforms that are
designed to have both, but have the RCS engine fused off.

Various engine-centric initialization that only needs to be done a
single time for the group of RCS+CCS engines can't rely on being setup
with the RCS now; instead we add a I915_ENGINE_FIRST_RENDER_COMPUTE flag
that will be assigned to a single engine in the group; whichever engine
has this flag will be responsible for some of the general setup
(RCU_MODE programming, initialization of certain workarounds, etc.).

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220303223435.2793124-1-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index e1aa78b20d2dffa20848ea1445b9b437656812eb..d26cef970f404d394802f3619ac4982a2e20c7c4 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -434,6 +434,11 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
        if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
                engine->props.preempt_timeout_ms = 0;
 
+       if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) &&
+            __ffs(CCS_MASK(engine->gt)) == engine->instance) ||
+            engine->class == RENDER_CLASS)
+               engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE;
+
        /* features common between engines sharing EUs */
        if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
                engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 19ff8758e34de3fa5fb872fadbbb20dcea26966f..4fbf45a74ec0719da972f0ab185f66dd5222b711 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -97,6 +97,7 @@ struct i915_ctx_workarounds {
 #define I915_MAX_VCS   8
 #define I915_MAX_VECS  4
 #define I915_MAX_CCS   4
+#define I915_MAX_RCS   1
 
 /*
  * Engine IDs definitions.
@@ -526,6 +527,7 @@ struct intel_engine_cs {
 #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
 #define I915_ENGINE_HAS_RCS_REG_STATE  BIT(9)
 #define I915_ENGINE_HAS_EU_PRIORITY    BIT(10)
+#define I915_ENGINE_FIRST_RENDER_COMPUTE BIT(11)
        unsigned int flags;
 
        /*

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 3e0c81f06bd040c1b3d41cede60c57c2acd3f8ee..ba42bede183ca48149eea8868d7523d0cf413f1f 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2911,7 +2911,7 @@ static int execlists_resume(struct intel_engine_cs *engine)
 
        enable_execlists(engine);
 
-       if (engine->class == RENDER_CLASS)
+       if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)
                xehp_enable_ccs_engines(engine);
 
        return 0;

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index c014b40d2e9f794cc72001b1ee9cf81c616bc58f..beca8735bae5828e68a837b54c0941854b6daa8c 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2633,7 +2633,7 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal
         * to a single RCS/CCS engine's workaround list since
         * they're reset as part of the general render domain reset.
         */
-       if (engine->class == RENDER_CLASS)
+       if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)
                general_render_compute_wa_init(engine, wal);
 
        if (engine->class == RENDER_CLASS)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 9bb551b83e7adeb814fc41e00cc8f83c623a141f..32c2053f2f08d3e6225b7be2cd02095564793b2a 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -335,7 +335,7 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
        ret |= GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false);
        ret |= GUC_MMIO_REG_ADD(regset, RING_IMR(base), false);
 
-       if (engine->class == RENDER_CLASS &&
+       if ((engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) &&
            CCS_MASK(engine->gt))
                ret |= GUC_MMIO_REG_ADD(regset, GEN12_RCU_MODE, true);
 

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 9d8a271b7a24405bf9e6e834f24eac3d208e0986..9ec03234d2c252fbdb9f602cf8619503c098496e 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3616,7 +3616,7 @@ static int guc_resume(struct intel_engine_cs *engine)
        setup_hwsp(engine);
        start_engine(engine);
 
-       if (engine->class == RENDER_CLASS)
+       if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)
                xehp_enable_ccs_engines(engine);
 
        return 0;

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d134838b3458e75854a4b93cff88d0e3154fb091..57643639b09220d6370add6e0b57ecf6fedf410f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1237,6 +1237,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
        ((gt)->info.engine_mask &                                               \
         GENMASK(first__ + count__ - 1, first__)) >> first__;           \
 })
+#define RCS_MASK(gt) \
+       ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
 #define VDBOX_MASK(gt) \
        ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
 #define VEBOX_MASK(gt) \