[POWERPC] QE: pario - support for MPC85xx layout

8 bytes padding required to match MPC85xx registers layout.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
index a114cb0c572fb46ab90e26ba8f572f7f6a02b608..e53ea4d374a03f52f57c6e9c5e036275fb207c0b 100644 (file)
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -36,6 +36,9 @@ struct port_regs {
        __be32  cpdir2;         /* Direction register */
        __be32  cppar1;         /* Pin assignment register */
        __be32  cppar2;         /* Pin assignment register */
+#ifdef CONFIG_PPC_85xx
+       u8      pad[8];
+#endif
 };
 
 static struct port_regs *par_io = NULL;