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(parent: fd617a6) | patch
drm/amdgpu: Add CLK IP base offset
authorRex Zhu <rex.zhu@amd.com>
Thu, 5 Jul 2018 08:34:13 +0000 (16:34 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 10 Jul 2018 19:16:39 +0000 (14:16 -0500)
commitfe0bad41092912f256fa718b5e1ce8ae2a51960a
treef17d07fe289e897ad5245eb6a80252841cb3803ctree | snapshot
parentfd617a651b0d56cf79871ff0b253ce1ed18bce39commit | diff
drm/amdgpu: Add CLK IP base offset

so we can read/write the registers in CLK domain
through RREG32/WREG32_SOC15

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h diff | blob | history
drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c diff | blob | history
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