]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915: Increase WM memory latency values on SNB
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 8 May 2014 12:09:19 +0000 (15:09 +0300)
committerJani Nikula <jani.nikula@intel.com>
Thu, 15 May 2014 11:10:11 +0000 (14:10 +0300)
commitfc1ee7da2a4cb496978257fc5a1d8bc3353259d7
tree51fb462adf74b1472a4e82f4858c393321743e7a
parentfee3779f4a8ec98bf9c8fe9b1218b9c16f4b88d2
drm/i915: Increase WM memory latency values on SNB

On SNB the BIOS provided WM memory latency values seem insufficient to
handle high resolution displays.

In this particular case the display mode was a 2560x1440@60Hz, which
makes the pixel clock 241.5 MHz. It was empirically found that a memory
latency value if 1.2 usec is enough to avoid underruns, whereas the BIOS
provided value of 0.7 usec was clearly too low. Incidentally 1.2 usec
is what the typical BIOS provided values are on IVB systems.

Increase the WM memory latency values to at least 1.2 usec on SNB.
Hopefully this won't have a significant effect on power consumption.

v2: Increase the latency values regardless of the pixel clock

Cc: Robert N <crshman@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70254
Tested-by: Robert Navarro <crshman@gmail.com>
Tested-by: Vitaly Minko <vitaly.minko@gmail.com>
Cc: stable@vger.kernel.org
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/intel_pm.c