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(parent: dddd68a) | patch
drivers/perf: fsl_imx8_ddr: Correct the CLEAR bit definition
authorJoakim Zhang <qiangqing.zhang@nxp.com>
Tue, 25 Feb 2020 12:56:43 +0000 (20:56 +0800)
committerWill Deacon <will@kernel.org>
Mon, 2 Mar 2020 12:07:19 +0000 (12:07 +0000)
commitfbee0cba872c02ae1b1dfe057657dbc0819c21f1
tree7a1fa34cf4825d70c3bbdef0c9b9d6760f0abe75tree | snapshot
parentdddd68ab6b6cbe4dfe8ced837cdd28813aec9f1acommit | diff
drivers/perf: fsl_imx8_ddr: Correct the CLEAR bit definition

When disabling a counter from ddr_perf_event_stop(), the counter value
is reset to 0 at the same time.

Preserve the counter value by performing a read-modify-write of the
PMU register and clearing only the enable bit.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Will Deacon <will@kernel.org>
drivers/perf/fsl_imx8_ddr_perf.c diff | blob | history
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