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(parent: ba288e1) | patch
clk: tegra: move from a lock bit idx to a lock mask
authorPeter De Schrijver <pdeschrijver@nvidia.com>
Wed, 3 Apr 2013 14:40:40 +0000 (17:40 +0300)
committerStephen Warren <swarren@nvidia.com>
Thu, 4 Apr 2013 22:10:49 +0000 (16:10 -0600)
commitfbb8c7779e94ed4ca492f31b9686569d3c839d06
tree5bb1543197683bdcaf8c8b4c5221147f717a7b6ftree | snapshot
parentba288e1927427dca26775b0ca6b5456ccb991a10commit | diff
clk: tegra: move from a lock bit idx to a lock mask

PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
drivers/clk/tegra/clk-pll.c diff | blob | history
drivers/clk/tegra/clk-tegra20.c diff | blob | history
drivers/clk/tegra/clk-tegra30.c diff | blob | history
drivers/clk/tegra/clk.h diff | blob | history
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