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arm64: dts: allwinner: a64: Add L2 cache nodes
authorAndre Przywara <andre.przywara@arm.com>
Mon, 30 Jul 2018 12:31:19 +0000 (13:31 +0100)
committerChen-Yu Tsai <wens@csie.org>
Mon, 27 Aug 2018 07:42:52 +0000 (15:42 +0800)
commitfaf7b91649f071d9733f2b8d2c3e7292ebf5d126
tree5bca4ac8b775212b700637b2679f2a4ddafe082etree | snapshot
parent258f14db30856854e3b5dc22bb033f7cbde7f359commit | diff
arm64: dts: allwinner: a64: Add L2 cache nodes

Current kernels complain when booting on an A64 Soc:
....
[    1.904297] cacheinfo: Unable to detect cache hierarchy for CPU 0
....
Not a real biggie on this flat topology, but also easy enough to fix.

Add the L2 cache node and let each CPU point to it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi diff | blob | history
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