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(parent: 64c6f04) | patch
can: flexcan: add quirk FLEXCAN_QUIRK_ENABLE_EACEN_RRS
authorMarc Kleine-Budde <mkl@pengutronix.de>
Tue, 1 Sep 2015 06:57:55 +0000 (08:57 +0200)
committerMarc Kleine-Budde <mkl@pengutronix.de>
Mon, 6 Feb 2017 14:13:42 +0000 (15:13 +0100)
commitf78b5390321a01e13dcba414f26767f719cbed53
tree33826e4957f696a23f55d007d71a44490082b5bdtree | snapshot
parent64c6f044a61e2a505d74b98b98dc94c5769febe8commit | diff
can: flexcan: add quirk FLEXCAN_QUIRK_ENABLE_EACEN_RRS

In order to receive RTR frames in the non HW FIFO mode the RSS and EACEN bits
of the reg_ctrl2 have to be activated. As this has no side effect in the FIFO
mode, we do this unconditionally on cores with the reg_ctrl2.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
drivers/net/can/flexcan.c diff | blob | history
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