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(parent: 863f539) | patch
drm/tegra: dpaux: Registers are 32-bit
authorThierry Reding <treding@nvidia.com>
Tue, 2 Jun 2015 11:13:01 +0000 (13:13 +0200)
committerThierry Reding <treding@nvidia.com>
Fri, 12 Jun 2015 14:26:04 +0000 (16:26 +0200)
commitf3b13863eca043181342db05046aa1f9370a7657
tree4bb8b985a8c62ad80e531d8aa393a368546510fftree | snapshot
parent863f5398653ab1bbb8cdaa22ca81427cae0ba7ddcommit | diff
drm/tegra: dpaux: Registers are 32-bit

Use a sized unsigned 32-bit data type (u32) to store register contents.
The DPAUX registers are 32 bits wide irrespective of the architecture's
data width.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/drm/tegra/dpaux.c diff | blob | history
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