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(parent: e4cd5d2) | patch
MIPS: Disable usermode switching of the FR bit for MIPS R5 CPUs.
authorRalf Baechle <ralf@linux-mips.org>
Thu, 19 Sep 2013 09:15:49 +0000 (11:15 +0200)
committerRalf Baechle <ralf@linux-mips.org>
Thu, 19 Sep 2013 09:23:10 +0000 (11:23 +0200)
commite5e8353dfe038a6058001151bb5f80f4bbd296e7
tree8559e2a5ba5149aff5079713e28945b226faca96tree | snapshot
parente4cd5d2c826d2bf588c2ac962773fe3cc01cdb9acommit | diff
MIPS: Disable usermode switching of the FR bit for MIPS R5 CPUs.

Currently the kernel will always use the FR=0 register model for O32.  If
an O32 application did enable FR=1 mode, some data from another application
might be leaked in the extra registers becoming visible.

Iow, this patch is meant to make the kernel MIPS R5 tolerant but leaves
proper MIPS R5 support to a future patchset.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/cpu-probe.c diff | blob | history
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