]> git.baikalelectronics.ru Git - kernel.git/commit
cxgb4/cxgb4vf: For T5 use Packing and Padding Boundaries for SGE DMA transfers
authorHariprasad Shenai <hariprasad@chelsio.com>
Fri, 7 Nov 2014 11:36:30 +0000 (17:06 +0530)
committerDavid S. Miller <davem@davemloft.net>
Mon, 10 Nov 2014 19:15:03 +0000 (14:15 -0500)
commite5200122f6fb470c24b71db25ef94dc692804794
treeadaef931f4064d2969ca78d987dccace85607d3a
parent9ac3c68a4cf04d1ff0b319722e62540b6e793ea0
cxgb4/cxgb4vf: For T5 use Packing and Padding Boundaries for SGE DMA transfers

T5 introduces the ability to have separate Packing and Padding Boundaries
for SGE DMA transfers from the chip to Host Memory. This change set takes
advantage of that to set up a smaller Padding Boundary to conserve PCI Link
and Memory Bandwidth with T5.

Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/chelsio/cxgb4/sge.c
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
drivers/net/ethernet/chelsio/cxgb4vf/sge.c
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_common.h
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c