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(parent: 568b6a1) | patch
drm/i915/tgl: Add Wa_1409825376 to tgl
authorRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Thu, 9 Jan 2020 22:37:27 +0000 (14:37 -0800)
committerMatt Roper <matthew.d.roper@intel.com>
Wed, 15 Jan 2020 16:29:07 +0000 (08:29 -0800)
commitdc6a3ddcfe54d5eb167a20d182b855790acf4445
tree0cab92a14b3a4ecfbf3f7f61272dd03040768f10tree | snapshot
parent568b6a1f4f2c2039a6be44ba9a8bf22cf6e9b637commit | diff
drm/i915/tgl: Add Wa_1409825376 to tgl

Workaround database indicates we should disable VRH clockgating
in pre-production hardware.

V2:
 - Use REG_BIT macro
 - Update reference in commit message(Matt)

Bspec: 52890
Bspec: 49424
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200109223727.5630-1-radhakrishna.sripada@intel.com
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
drivers/gpu/drm/i915/intel_pm.c diff | blob | history
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