]> git.baikalelectronics.ru Git - kernel.git/commit
projects / kernel.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: b9895df) | patch
clk: mediatek: Fix PLL registers setting flow
authorJames Liao <jamesjj.liao@mediatek.com>
Fri, 10 Jul 2015 08:39:32 +0000 (16:39 +0800)
committerStephen Boyd <sboyd@codeaurora.org>
Tue, 28 Jul 2015 18:58:52 +0000 (11:58 -0700)
commitdb12dff7b470a59f1e0f49595d4d0fee3fdec3b2
tree427efcbd2d64d3d21b2642289c89f4e6b3142bc3tree | snapshot
parentb9895df9936a88423a46c55d8515474a531cc051commit | diff
clk: mediatek: Fix PLL registers setting flow

Write postdiv and pcw settings at the same time for PLLs if postdiv
and pcw settings are on the same register.

This is need by PLLs such as MT8173 MMPLL and ARM*PLL.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/mediatek/clk-pll.c diff | blob | history
Linux Kernel Source Tree.