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RISC-V: KVM: Add Sv57x4 mode support for G-stage
authorAnup Patel <apatel@ventanamicro.com>
Mon, 9 May 2022 05:13:39 +0000 (10:43 +0530)
committerAnup Patel <anup@brainfault.org>
Fri, 20 May 2022 03:39:04 +0000 (09:09 +0530)
commitdaea8fc017564851cb81a1892a7aae62e08a9436
treec9d418c9a33ea8c27db1e8155501ccb3b1236148tree | snapshot
parentf64fcc44b8ceecea807f8dc0d824ae18d0a9c6b4commit | diff
RISC-V: KVM: Add Sv57x4 mode support for G-stage

Latest QEMU supports G-stage Sv57x4 mode so this patch extends KVM
RISC-V G-stage handling to detect and use Sv57x4 mode when available.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/asm/csr.h diff | blob | history
arch/riscv/kvm/main.c diff | blob | history
arch/riscv/kvm/mmu.c diff | blob | history
Linux Kernel Source Tree.