]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915: Reduce CHV DPLL min vco frequency to 4.8 GHz
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 26 Feb 2015 19:01:52 +0000 (21:01 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 17 Mar 2015 21:29:52 +0000 (22:29 +0100)
commitd82be993911352d1d3dcfad1a5aea02e38aef696
tree89dd3f461e5191292b5d44ce0e9f2a54f631e144
parent963629aa414d3713ded2d375f63968cd5352eba3
drm/i915: Reduce CHV DPLL min vco frequency to 4.8 GHz

The current minimum vco frequency leaves us with a gap in our supported
frequencies at 233-243 MHz. Your typical 2560x1440@60 display wants a
pixel clock of 241.5 MHz, which is just withing that gap. Reduce the
allowed vco min frequency to 4.8GHz to reduce the gap to 233-240 MHz,
and thus allow such displays to work.

4.8 GHz is actually the documented (at least in some docs) limit of the
PLL, and we just picked 4.86 GHz originally because that was the lowest
value produced by the PLL spreadsheet, which obviously didn't consider
2560x1440 displays.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c