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(parent: e4f85c2) | patch
drm/amd/display: add new pixel rate programming
authorJun Lei <Jun.Lei@amd.com>
Sun, 20 Feb 2022 18:58:51 +0000 (13:58 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 3 Jun 2022 20:45:01 +0000 (16:45 -0400)
commitd7cf9536f1c41c1b25777e69898f291db924ffb4
tree46c7513a070155f507999902ad5bec6d8e5f23abtree | snapshot
parente4f85c248605e51b61a90ec2bde69f406b467d7acommit | diff
drm/amd/display: add new pixel rate programming

[why]
New dividers in DCCG need to be programmed depending
on encoder/stream type since pixels per clock in
OTG/DIO is different

DIO also needs additional programming depending on
pixels per clock

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.h diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c diff | blob | history
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h diff | blob | history
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h diff | blob | history
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h diff | blob | history
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