]> git.baikalelectronics.ru Git - kernel.git/commit
memory: omap-gpmc: Support WAIT pin edge interrupts
authorRoger Quadros <rogerq@ti.com>
Fri, 19 Feb 2016 09:01:02 +0000 (11:01 +0200)
committerRoger Quadros <rogerq@ti.com>
Fri, 15 Apr 2016 08:55:06 +0000 (11:55 +0300)
commitcf2801c920c4eaf53b3cbfc39ce8b62920eeba57
treef8bf795b115860f570f179f3ee65ffa6b992a0a8
parent0def8b5e1adc1f5baf7301888a4f5824049c9e8b
memory: omap-gpmc: Support WAIT pin edge interrupts

OMAPs can have 2 to 4 WAITPINs that can be used as edge triggered
interrupts if not used for memory wait state insertion.

Support these interrupts via the gpmc IRQ domain.

The gpmc IRQ domain interrupt map is:

0 - NAND_fifoevent
1 - NAND_termcount
2 - GPMC_WAIT0 edge
3 - GPMC_WAIT1 edge, and so on

Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
drivers/memory/omap-gpmc.c