]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915: Re-enable per-engine reset for Broxton
authorMichel Thierry <michel.thierry@intel.com>
Fri, 18 Aug 2017 17:23:42 +0000 (10:23 -0700)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 22 Aug 2017 11:27:18 +0000 (12:27 +0100)
commitcc76e7b6750ae637254812a0c82be2f059117ea6
treeb096c6a0e27a68c869053d7e1378a55d45a5d956
parent7b9260013364646191b0238709a3c4f957650263
drm/i915: Re-enable per-engine reset for Broxton

The corruption in CSB mmio reads we were seeing has been tracked down to
incorrectly touching forcewake of all domains, following an engine reset.
It is still a mistery why we only catched this in Broxton, since it
could happen in any platform.

With that fix already merged, commit 37c34927e792 ("drm/i915: Stop
touching forcewake following a gen6+ engine reset"), lets try to enable
per-engine resets in Broxton one more time.

This reverts commit f188258bde0f ("drm/i915: Disable per-engine reset for
Broxton").

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170818172342.7282-1-michel.thierry@intel.com
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/gpu/drm/i915/i915_pci.c