]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported
authorManasi Navare <manasi.d.navare@intel.com>
Wed, 31 Oct 2018 00:19:22 +0000 (17:19 -0700)
committerManasi Navare <manasi.d.navare@intel.com>
Wed, 31 Oct 2018 21:10:08 +0000 (14:10 -0700)
commitca8fd63efdefa5ada32a2604ec54391e607993b3
treed8d5c97285c2d50cc045b1f92f2266c78f38e242
parent522c0cf2eb72ec17d55a036d4639ab08d0ffdf0a
drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported

When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compressed BPP
and slice count requirements.

v3:
* Use the macro for dsc sink support (Jani N)
v2:
* Properly comment why we are right shifting the bpp value (Anusha)

Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181031001923.31442-6-manasi.d.navare@intel.com
drivers/gpu/drm/i915/intel_dp.c