]> git.baikalelectronics.ru Git - kernel.git/commit
drm/msm/dpu: Avoid ABBA deadlock between IRQ modules
authorBjorn Andersson <bjorn.andersson@linaro.org>
Fri, 11 Jun 2021 17:00:03 +0000 (10:00 -0700)
committerRob Clark <robdclark@chromium.org>
Wed, 23 Jun 2021 14:33:55 +0000 (07:33 -0700)
commitc96348a8fbff90ef610b0323218e9d585683bdd2
treed4d604dc8d3a0d9c1af7b19a3a894448b30af250
parente25e92e08e32c6bf63a968929d232f13dcf9938c
drm/msm/dpu: Avoid ABBA deadlock between IRQ modules

Handling of the interrupt callback lists is done in dpu_core_irq.c,
under the "cb_lock" spinlock. When these operations results in the need
for enableing or disabling the IRQ in the hardware the code jumps to
dpu_hw_interrupts.c, which protects its operations with "irq_lock"
spinlock.

When an interrupt fires, dpu_hw_intr_dispatch_irq() inspects the
hardware state while holding the "irq_lock" spinlock and jumps to
dpu_core_irq_callback_handler() to invoke the registered handlers, which
traverses the callback list under the "cb_lock" spinlock.

As such, in the event that these happens concurrently we'll end up with
a deadlock.

Prior to '1c1e7763a6d4 ("drm/msm/dpu: simplify IRQ enabling/disabling")'
the enable/disable of the hardware interrupt was done outside the
"cb_lock" region, optimitically by using an atomic enable-counter for
each interrupt and an warning print if someone changed the list between
the atomic_read and the time the operation concluded.

Rather than re-introducing the large array of atomics, this change
embraces the fact that dpu_core_irq and dpu_hw_interrupts are deeply
entangled and make them share the single "irq_lock".

Following this step it's suggested that we squash the two parts into a
single irq handling thing.

Fixes: 1c1e7763a6d4 ("drm/msm/dpu: simplify IRQ enabling/disabling")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210611170003.3539059-1-bjorn.andersson@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h