]> git.baikalelectronics.ru Git - kernel.git/commit
net: phy: marvell: configure RGMII delays for 88E1118
authorRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Tue, 4 Jan 2022 16:38:19 +0000 (16:38 +0000)
committerJakub Kicinski <kuba@kernel.org>
Wed, 5 Jan 2022 18:30:30 +0000 (10:30 -0800)
commitc8c2e2fa481c3871e6ba252651642f794bf2ff69
tree8e3714a58d7b06d512d846b7012c6abbe59275b3
parentb48109be068dbb015f21582ea01301a3c10f7b05
net: phy: marvell: configure RGMII delays for 88E1118

Corentin Labbe reports that the SSI 1328 does not work when allowing
the PHY to operate at gigabit speeds, but does work with the generic
PHY driver.

This appears to be because m88e1118_config_init() writes a fixed value
to the MSCR register, claiming that this is to enable 1G speeds.
However, this always sets bits 4 and 5, enabling RGMII transmit and
receive delays. The suspicion is that the original board this was
added for required the delays to make 1G speeds work.

Add the necessary configuration for RGMII delays for the 88E1118 to
bring this into line with the requirements for RGMII support, and thus
make the SSI 1328 work.

Corentin Labbe has tested this on gemini-ssi1328 and gemini-ns2502.

Reported-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/phy/marvell.c