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(parent: 9238ecf) | patch
clk: meson: mpll: fix mpll0 fractional part ignored
authorJerome Brunet <jbrunet@baylibre.com>
Fri, 28 Jul 2017 16:32:28 +0000 (18:32 +0200)
committerNeil Armstrong <narmstrong@baylibre.com>
Tue, 1 Aug 2017 12:18:31 +0000 (14:18 +0200)
commitc86468257f131e99012877b51c68c51636d3a2cb
treec7b8e973a1121f26b9f4f0f53277fac73ca5273ctree | snapshot
parent9238ecfbaaeffcf7977c2776af9c57c0a4a878edcommit | diff
clk: meson: mpll: fix mpll0 fractional part ignored

mpll0 clock is special compared to the other mplls. It needs another
bit (ssen) to be set to activate the fractional part the mpll divider

Fixes: a1be91571e28 ("clk: meson: mpll: add rw operation")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
drivers/clk/meson/clk-mpll.c diff | blob | history
drivers/clk/meson/clkc.h diff | blob | history
drivers/clk/meson/gxbb.c diff | blob | history
drivers/clk/meson/meson8b.c diff | blob | history
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