]> git.baikalelectronics.ru Git - kernel.git/commit
dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache
authorZong Li <zong.li@sifive.com>
Tue, 13 Sep 2022 06:18:11 +0000 (06:18 +0000)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 13 Oct 2022 18:06:50 +0000 (11:06 -0700)
commitc51e66936ad33b37fbaa29b82337c1a6cdcf99d7
treef08af1f2214ae8cc4834c04d575f0ef316ac3b5d
parent609fb31e0955d77e7029ccd2993c082211b02be1
dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache

Since composable cache may be L3 cache if private L2 cache exists, we
should use its original name Composable cache to prevent confusion.

Signed-off-by: Zong Li <zong.li@sifive.com>
Suggested-by: Conor Dooley <conor.dooley@microchip.com>
Suggested-by: Ben Dooks <ben.dooks@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220913061817.22564-2-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml [new file with mode: 0644]
Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml [deleted file]