]> git.baikalelectronics.ru Git - uboot.git/commit
riscv: Add CSR numbers
authorBin Meng <bmeng.cn@gmail.com>
Wed, 12 Dec 2018 14:12:36 +0000 (06:12 -0800)
committerAndes <uboot@andestech.com>
Tue, 18 Dec 2018 01:56:27 +0000 (09:56 +0800)
commitc48ab183e1122d2518a9120bece9aef8f2e110c2
treeca62776a9b1f04df964623b80df6dd1dd8594546
parentdf32632777532a900d1bb4b6360c1aae1aeb63c9
riscv: Add CSR numbers

The standard RISC-V ISA sets aside a 12-bit encoding space for up
to 4096 CSRs. This adds all known CSR numbers as defined in the
RISC-V Privileged Architecture Version 1.10.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/asm/encoding.h