drm/tegra: dsi: Set up PHY_TIMING & BTA_TIMING registers earlier

drm/tegra: dsi: Set up PHY_TIMING & BTA_TIMING registers earlier

Make sure the DSI PHY_TIMING and BTA_TIMING registers are initialized
when the clocks are set up as opposed to when the output is enabled.
This makes sure that the PHY timings are properly set up when the panel
is prepared and that DCS commands sent at that time use the appropriate
timings.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>