]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915: Enable PCH FIFO underruns later on HSW+
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 29 Oct 2015 19:25:53 +0000 (21:25 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 10 Nov 2015 14:23:06 +0000 (16:23 +0200)
commitbeb821c39b36c72131a2d2fad6e177ed48f35927
tree5e2925f4f2b8b889902c82ed97354e1fad0c6746
parentee1b5cfe6daecf7cd37af5fa60cddfbc96ecedf2
drm/i915: Enable PCH FIFO underruns later on HSW+

As we did for ILK/SNB/IVB, move the PCH FIFO underrun enable to happen
after the encoder enable on HSW+. And again, for symmetry, move the
the disable to happen before encoder disable.

I've left out the vblank wait before the enable here because I don't
know if it's needed or not. Actually I don't know if this entire
change is needed as I don't have a HSW/BDW with VGA output.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446146763-31821-5-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
drivers/gpu/drm/i915/intel_display.c