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(parent: 653f987) | patch
mlxsw: reg: Add counter fields to RITR register
authorArkadi Sharshevsky <arkadis@mellanox.com>
Tue, 28 Mar 2017 15:24:11 +0000 (17:24 +0200)
committerDavid S. Miller <davem@davemloft.net>
Wed, 29 Mar 2017 00:11:54 +0000 (17:11 -0700)
commitbc2d283f179fdedf57ae8268e01463ab589fc8ad
treec39071828e549a5a1dc337a55cfd855c1b164c8dtree | snapshot
parent653f9875926304a6f88a91ceb94389f50618b60bcommit | diff
mlxsw: reg: Add counter fields to RITR register

Update RITR for counter support. This allows adding counters for
ASIC's router ports.

Signed-off-by: Arkadi Sharshevsky <arkadis@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/mellanox/mlxsw/reg.h diff | blob | history
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